Motorola PowerQUICC II MPC8280 Series Reference Manual page 1317

Table 36-2. Ethernet-Specific Parameter RAM (continued)
1
Offset Name Width
0x68 TFCSTAT Hword Out-of-sequence TxBD. Includes the status/control, data length, and buffer pointer
0x6A TFCLEN Hword
0x6C TFCPTR Word
0x70 MFLR Hword Maximum frame length register (typically1518 decimal). If the Ethernet controller
0x72 PADDR1_H Hword The 48-bit individual address of this station. PADDR1_L is the lowest order half-word,
0x74 PADDR1_M Hword
0x76 PADDR1_L Hword
0x78 IBD_CNT Hword Internal BD counter
0x7A IBD_START Hword Internal BD start pointer
0x7C IBD_END Hword Internal BD end pointer
0x7E TX_LEN Hword Tx frame length counter
0x80 IBD_BASE 32
Bytes
0xA0 IADDR_H Word Individual address filter high/low. Used in the hash table function of the individual
0xA4 IADDR_L Word
0xA8 MINFLR Hword Minimum frame length register (typically 64 decimal). If the Ethernet receiver detects
0xAA TADDR_H Hword Allows addition of addresses to the individual and group hashing tables. After an
0xAC TADDR_M Hword
0xAE TADDR_L Hword
0xB0 PAD_PTR Hword Internal PAD pointer. This internal 32-byte aligned pointer points to a 32-byte buffer
0xB2 — Hword Reserved, should be cleared.
0xB4 CF_RANGE Hword Control frame range. Internal usage
0xB6 MAX_B Hword Maximum BD byte count. Internal usage
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fields in the same format as a regular TxBD. Useful for sending flow control frames.
This area's TxBD[R] is always checked between frames, regardless of FPSMRx[FCE].
If it is not ready, a regular frame is sent. The user must set TxBD[L] when preparing
this BD. If TxBD[I] is set, a TXC event is generated after frame transmission. This area
should be cleared when not in use.
detects an incoming frame exceeding MFLR, it sets RxBD[LG] (frame too long) in the
last RxBD, but does not discard the rest of the frame. The controller also reports the
frame status and length of the received frame in the last RxBD. MFLR includes all
in-frame bytes between the start frame delimiter and the end of the frame.
and PADDR1_H is the highest order half-word.
Internal microcode usage
addressing mode. The user can write zeros to these values after reset and before the
Ethernet channel is enabled to disable all individual hash address recognition
functions. Issuing a
SET GROUP ADDRESS
Section 36.13, "Hash Table Algorithm."
an incoming frame shorter than MINFLR, it discards that frame unless FPSMR[RSH]
(receive short frames) is set, in which case RxBD[SH] (frame too short) is set in the
last RxBD. The Ethernet transmitter pads frames that are too short (according to
TxBD[PAD] and the PAD value in the parameter RAM). PADs are added to make the
transmit frame MINFLR bytes.
address is placed in TADDR, issue a
lowest-order half-word; TADDR_H is the highest.
A zero in the I/G bit indicates an individual address; 1 indicates a group address.
filled with pad characters. The pads may be any value, but all the bytes should be the
same to assure padding with a specific character. If a specific padding character is not
needed, PAD_PTR should equal the internal temporary data pointer TIPTR; see
Section 30.7, "FCC Parameter RAM."
Chapter 36. Fast Ethernet Controller
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Ethernet Parameter RAM
Description
command enables the hash table. See
command. TADDR_L is the
SET GROUP ADDRESS
36-11