Motorola PowerQUICC II MPC8280 Series Reference Manual page 1150

Receive and Transmit Connection Tables (RCT, TCT)
Table 32-5. RCT Field Descriptions (continued)
Offset Bits Name
0x04 — RxDBPTR
0x08 — Cell Time
Stamp
0x0C — RBD_Offset
0x0E-0 —
x18
0x1A — MRBLR
0x1C 0–1 —
2–7 PMT
8–15 RBD_BASE
0x1E 0–11
12 CCASM
13 CESM
14 —
15 PM
32.9.1.1 AAL1 CES Protocol-Specific RCT
Figure 32-22 shows the AAL1 CES protocol-specific area of an RCT entry.
0 1
Offset + 0x0E SRTS_DEV
Offset + 0x10
OCASB/SRTS_TMP
Offset + 0x12 SPV
Offset + 0x14
Offset + 0x16
Offset + 0x18
Figure 32-22. AAL1 CES Protocol-Specific RCT
32-30
Freescale Semiconductor, Inc.
Receive data buffer pointer. Holds real address of current position in the Rx buffer.
Used for reassembly time-out. Whenever a cell is received, the MPC8280 time stamp
timer is sampled and written to this field. See Section 14.3.8, "RISC Time-Stamp
Control Register (RTSCR)."
RxBD offset from RBD_BASE. Points to the channel's current BD. User-initialized to 0;
updated by the CP.
Protocol-specific area.
Maximum receive buffer length. Used in both static and dynamic buffer allocation.
Note that in CES mode (CESM=1) this value must be a multiple of 8 (MCC limited).
Reserved, should be cleared during initialization.
Performance monitoring table. Points to one of the available 64 performance
monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be
changed on-the-fly.
RxBD base. Points to the first BD in the channel's RxBD table. The 8 most-significant
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four
least-significant bits of the address are taken as zeros.
Core CAS modify. When this mode is enabled, the CP sets OCASSR[MCASBn] sticky
bit each time the outgoing (ATM to TDM) CAS block is changed.
0 Core CAS modify mode is disabled.
1 Core CAS modify mode is enabled.
See Section 32.10, "Outgoing CAS Status Register (OCASSR)."
Circuit Emulation Service Mode.
0 CES operation mode is disable. Adaptive Slip control mechanism is disabled.
1 CES operation mode is enable. Adaptive Slip control mechanism is enabled.
Reserved, should be cleared during initialization.
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received for this VC
the performance monitoring table that its code is written in the PMT field is updated.
2 3 4 5 6
—
—
—
Block Size
Super Channel Number
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Description
7 8 9 10
PFM SRT INVE STF
—
Structured Pointer (SP)
RBDCNT
RXBM SLIPIM
—
11 12 13 14 15
—
Valid Octet Size (VOS)
SN
—
CASBS
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