Motorola PowerQUICC II MPC8280 Series Reference Manual page 1085

Figure 31-42 shows the empty bit in the RxBD tables and their associated buffers for two
example ATM channels.
Ch1 RxBD Table
Pointers in the RCT
Ch4 RxBD Table
Pointers in the RCT
Note: The shaded buffers are empty; unshaded buffers are waiting to be processed.
Figure 31-42. Receive Static Buffer Allocation Example
31.10.5.2.2 Global Buffer Allocation
The user prepares a table of BDs without assigning buffers to them (no buffer pointers). The
address of the first BD is put into the channel's RCT[RBD_BASE]. The user also prepares
sets of free buffers (of size RCT[MRBLR]) in up to four free buffer pools (chosen in
RCT[BPOOL]); see Section 31.10.5.2.3, "Free Buffer Pools."
When an ATM cell arrives, the CP opens the first BD in the table, fetches a buffer pointer
from the free buffer pool associated with this channel, and writes the pointer to
RxBD[RXDBPTR], the receive data buffer pointer field in the BD. When the current buffer
is full, the CP increments RBD_Offset, which is the offset from the RBD_BASE to the
current BD, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP
fetches another buffer pointer from the free buffer pool and reception continues. If the BD
is not empty, a busy condition occurs and a busy interrupt is sent to the event queue
specifying the ATM channel code. As software then processes each full buffer (RxBD[E]
= 0), it sets RxBD[E] and copies the buffer pointer back to the free buffer pool.
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Ch1 RxBD Table
RBD_BASE
0
RBD_Offset
1
1
0
0
Ch4 RxBD Table
RBD_BASE
1
0
0
0
0
RBD_Offset
1
1
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Rx Buffer 1 of Channel 1
BD 1 Rx Buffer 2 of Channel 1
BD 2
Rx Buffer 3 of Channel 1
BD 3
BD 4
Rx Buffer 4 of Channel 1
BD 5
Rx Buffer 5 of Channel 1
Rx Buffer 1 of Channel 4
BD 1 Rx Buffer 2 of Channel 4
BD 2
Rx Buffer 3 of Channel 4
BD 3
BD 4
Rx Buffer 4 of Channel 4
BD 5
Rx Buffer 5 of Channel 4
BD 6
BD 7
Rx Buffer 6 of Channel 4
Rx Buffer 7 of Channel 4
ATM Memory Structure
31-71