Motorola PowerQUICC II MPC8280 Series Reference Manual page 1338

Key Features
37.1 Key Features
Key features of the HDLC include the following:
• Flexible data buffers with multiple buffers per frame
• Separate interrupts for frames and buffers (receive and transmit)
• Received frames threshold to reduce interrupt overhead
• Four address comparison registers with masks
• Maintenance of four 16-bit error counters
• Flag/abort/idle generation and detection
• Zero insertion/deletion
• 16- or 32-bit CRC-CCITT generation/checking
• Detection of nonoctet-aligned frames
• Detection of frames that are too long
• Programmable flags (0–15) between successive frames
• External BD table
• Up to T3 rate
• Support of time stamp mode for Rx frames
• Support of nibble mode HDLC (4 bits per clocks)
37.2 HDLC Channel Frame Transmission Processing
The HDLC transmitter is designed to work with almost no core intervention. When the core
enables a transmitter, it starts sending flags or idles as programmed in the HDLC mode
register (FPSMR). The HDLC controller polls the first BD in the transmit channel BD table.
When there is a frame to transmit, the HDLC controller fetches the data (address, control,
and information) from the first buffer and begins sending the frame after first inserting the
user-specified minimum number of flags between frames. When the end of the current
buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the CRC (if
selected) and closing flag. In HDLC, the lsb of each octet and the msb of the CRC are sent
first. Figure 37-1 shows a typical HDLC frame.
Opening Flag Address
8 Bits
After the closing flag is sent, the HDLC controller writes the frame status bits into the BD
and clears the R bit. When the end of the current BD is reached and the L (last) bit is not
37-2
Freescale Semiconductor, Inc.
Control Information (Optional)
16 Bits 8 Bits
Figure 37-1. HDLC Framing Structure
MPC8280 PowerQUICC II Family Reference Manual
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CRC
8n Bits 16 Bits
Closing Flag
8 Bits
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