Motorola PowerQUICC II MPC8280 Series Reference Manual page 1009

TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
Note:
1. A frame includes opening and closing flags and syncs, if present in the protocol.
Figure 30-9. Output Delay from RTS Asserted
If CTS is not already asserted when RTS is asserted, the delays to the first bit of data depend
on when CTS is asserted. Figure 30-10 shows that the delay between CTS and the data can
be approximately 0.5 to 1 bit times or no delay, depending on GFMR[CTSS].
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
Note:
1. GFMR[CTSS] = 0. CTSP is a don't care.
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
Note:
1. GFMR[CTSS] = 1. CTSP is a don't care.
Figure 30-10. Output Delay from CTS Asserted
If it is programmed to envelope the data, CTS must remain asserted during frame
transmission or a CTS lost error occurs. The negation of CTS forces RTS high and the
transmit data to the idle state. If GFMR[CTSS] = 0, the FCC must sample CTS before a
CTS lost is recognized. Otherwise, the negation of CTS immediately causes the CTS lost
condition. See Figure 30-11.
MOTOROLA Chapter 30. Fast Communications Controllers (FCCs)
Freescale Semiconductor, Inc.
First Bit of Frame Data
First Bit Of Frame Data
CTS Sampled Low
First Bit of Frame Data
For More Information On This Product,
Go to: www.freescale.com
Last Bit of Frame Data
Last Bit of Frame Data
Last Bit of Frame Data
FCC Timing Control
30-19