Motorola PowerQUICC II MPC8280 Series Reference Manual page 1445

GSMR_H,, 31-100, 31-101, 31-102
gsmr_h,, 31-100, 31-101, 31-102
H
HDLC mode
accessing the bus, 22-21
bus controller, 22-18
collision detection, 22-18, 22-22
commands, 22-5
delayed RTS mode, 22-23
error handling, 22-6
fast communications controllers (FCCs)
bit stuffing, 37-1
error control, 37-1
error handling, 37-6
FCCE, 37-14
FCCM, 37-14
FCCS, 37-16
features list, 37-2
FPSMR, 37-8
frame reception, 37-3
frame transmission, 37-2
overview, 37-1
parameter RAM, 37-4
programming model, 37-5
receive commands, 37-6
reception errors, 37-7
RxBD, 37-9
transmission errors, 37-7
transmit commands, 37-6
TxBD, 37-12
features list, 22-2
GSMR, HDLC bus protocol programming, 22-25
multi-master bus configuration, 22-20
overview, 22-1
parameter RAM, 22-3
performance, increasing, 22-22
programming example, 22-16, 22-25
programming the controller, 22-5
PSMR, 22-7
RxBD, 22-9
single-master bus configuration, 22-21
TxBD, 22-12
using the TSA, 22-24
HID0 register
bit settings, 2-12
doze, nap, sleep, DPM bits, 2-13
I
2
I2ADD (I C address) register, 40-7
2
I2BRG (I C baud rate generator) register, 40-8
2
I C controller
block diagram, 40-1
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BRGCLK, 40-2
clocking and pin functions, 40-2
commands, 40-12
features list, 40-2
loopback testing, 40-4
master read (slave write), 40-4
master write (slave read), 40-4
multi-master considerations, 40-5
parameter RAM, 40-9
programming model, 40-6
registers, 40-6
RxBD, 40-13
slave read (master write), 40-4
slave write (master read), 40-4
transfers, 40-3
TxBD, 40-14
I2C memory map,, 3-17
2
I2CER (I C event register), 40-8
2
I2CMR (I C mask register), 40-8
2
I2COM (I C command) register, 40-9
2
I2MOD (I C mode) register, 40-6
IDL interface programming,, 15-30
IDL interface support, 15-26
IDMA emulation
auto buffer, 19-17
buffer chaining, 19-17
buffers, 19-25
bus exceptions, 19-29
commands, 19-28
controlling 60x bus bandwidth, 19-13
DACKx, 19-15
DCM, 19-20
DONEx, 19-16
DREQx, 19-15
DTS/STS programming, 19-23
dual-address transfers, 19-11
edge-sensitive mode, 19-16
exception, bus, 19-29
external request mode, 19-9
features list, 19-6
IDMR, 19-25
IDSR, 19-25
level-sensitive mode, 19-16
normal mode, 19-10
operand transfers, recognizing, 19-30
operation, 19-17
overview, 19-5
parallel I/O register programming, 19-30
parameter RAM, 19-18
priorities, 19-14
programming examples, 19-31
programming the parallel I/O registers, 19-30
signals, 19-14
single address transfers (fly-by), 19-12
Index-11