Motorola PowerQUICC II MPC8280 Series Reference Manual page 1353

0
Field
Reset
R/W
Addr
Table 37-10 describes FCCS bits.
Table 37-10. FCCS Register Field Descriptions
Bits Name
0–4 — Reserved, should be cleared.
5 FG Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are
examined to see if a flag is present. FG is set as soon as an HDLC flag (0x7E) is received on the
line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined.
If another flag occurs, FG stays set for at least another eight bits. Otherwise, FG is cleared and the
search begins again.
• 0HDLC flags are not currently being received.
• 1HDLC flags are currently being received.
6 — Reserved, should be cleared.
7 ID Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is
cleared after a logic zero is received.
• 0The line is busy.
• 1The line is idle.
MOTOROLA
Freescale Semiconductor, Inc.
1 2 3
—
0x11318 (FCCS1), 0x11338 (FCCS2), 0x11358 (FCCS3)
Figure 37-9. FCC Status Register (FCCS)
Chapter 37. FCC HDLC Controller
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FCC Status Register (FCCS)
4 5
FG
0000_0000
R
Description
6 7
— ID
37-17