Motorola PowerQUICC II MPC8280 Series Reference Manual page 1293

octet. The result overwrites the HEC octet on the transmitted cell. When the transmit FIFO
is empty, the TCF inserts idle cells (counted in ICC).
The TCF accumulates the number of transmitted assigned cells in a counter (TCC).
35.2.2.1 Transmit ATM 2-Cell FIFO
The transmit FIFO provides FIFO management and an interface to the UTOPIA transmit
interface. The FIFO provides the cell rate decoupling between the transmission system
physical layer and the ATM layer.
The FIFO management includes emptying cells from the transmit FIFO, indicating to the
UTOPIA interface that it is full, maintaining the FIFO read and write pointers, and
detecting FIFO underrun (TCER[UR]) conditions.
35.2.3 Receive UTOPIA Interface
This block performs the receive interface with the FCC via the UTOPIA bus. It implements
the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface.
35.2.4 Transmit UTOPIA Interface
This block performs the transmit interface with the FCC via the UTOPIA bus. It
implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface.
35.3 Signals
The TC layer is operated via an SI TDM port using a serial protocol. Synchronization
signals are required for some applications and must be supported. Table 35-1 describes the
signals required for operating the TC layer.
Signal Direction
Txc Input Tx clock. Clocks Tx data out of the TC to external device.
Txd Output Tx data from TC to external device.
Txsyn Input Tx synch. Synchronizes the transmit data to the beginning of a frame.
Rxc Input Rx clock. Clocks the data into the TC.
Rxd Input Rx data. From external device to the TC.
Rxsyn Input Rx synch. Synchronizes the received data.
MOTOROLA
Freescale Semiconductor, Inc.
Table 35-1. TC Layer Signals
Chapter 35. ATM Transmission Convergence Layer
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Description
Signals
35-7