Motorola PowerQUICC II MPC8280 Series Reference Manual page 1130

Interworking Functions
received octet becomes the first byte of the new BD (new super frame). (Refer to
Section 32.5, "ATM-to-TDM Adaptive Slip Control.")
Note that when the ATM receiver is in hunt mode due to one of the following:
• Sequence number protection error (SNPE)
• Sequence count error (SCE)
• Structured pointer error (SPE)
• Slip condition
The signaling information (CAS) and SRTS information is not updated by the ATM
controller until the ATM receiver switches to SYNC mode, that is, a valid cell is received
in unstructured cell format or a valid pointer is received in structured cell formats.
Software should distinguish between the two types of overrun and underrun conditions:
6. The MCC and ATM controller can automatically recover from overruns and
underruns caused by slips without any CPU intervention. (See Section 32.5,
"ATM-to-TDM Adaptive Slip Control.")
7. Global underrun (MCCE[GUN]) and overrun (MCCE[GOV]) conditions are errors
that need CPU intervention because it is not known which channels are affected.
The CPU should accordingly reinitialize the transmit parameters and/or the receive
parameters to recover.
32.4.3 Clock Synchronization (SRTS, Adaptive FIFO)
Clock synchronization methods, such as SRTS and adaptive FIFO, may be used to prevent
reassembly buffer slip. The SRTS method may be implemented using external logic. The
MPC8280 can read the SRTS from external logic and insert it into outgoing AAL1 cells and
conversely, can track the SRTS from incoming AAL1 cells and deliver it to external logic.
See Section 31.16, "SRTS Generation and Clock Recovery Using External Logic."
Alternatively, an adaptive FIFO method can be implemented under core control. Adaptive
FIFO is a way to hold the bridging buffer at its mid-level point. One way to implement it is
to periodically poll the adaptive counter CESAC (difference between the MCC and ATM
data pointers) and use this difference as a pseudo-SRTS; see Section 32.5.1, "CES Adaptive
Threshold Tables." Writing the pseudo-SRTS to the same external PLL logic used in the
SRTS method adjusts the TDM clock.
32.4.4 Mapping TDM Time Slots to VCs
Any TDM time-slot combination can be routed to a specific data buffer using the MCC and
its SI. (Refer to Chapter 29, "Multi-Channel Controllers (MCCs)," and Chapter 15, "Serial
Interface with Time-Slot Assigner," for further information.) A common set of data buffers
(one BD table) should be used by the ATM controller to route both the receive and transmit
data. For information about ATM buffers see Section 32.11, "Buffer Descriptors."
32-10
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