Motorola PowerQUICC II MPC8280 Series Reference Manual page 1209

Table 33-14 describes the interrupt queue entry fields for a CID.
Table 33-14. AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions
Offset Bits Name
0x00 0 V
1 —
2 W
3–10 CID
11 TBNR
1
12 RXB
13 BSY
14 TXB
1
15 RXF
0x02 — CC
1
These interrupt queue fields are defined differently for other AAL types. Refer toTable 31-42 for more information.
An interrupt entry for the VC is shown in Figure 33-24.
.
0 1
Offset + 0x00 V —
Offset + 0x02
Figure 33-24. AAL2 Interrupt Queue Entry CID = 0
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Freescale Semiconductor, Inc.
Valid interrupt entry
0 This interrupt queue entry is free and can be used by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
—
Wrap bit. When set, this is the last interrupt entry in the circular table. During initialization,
the host must clear all W bits in the table except the last one, which must be set.
CID number. The exception occurred for this CID.
Tx buffer not ready interrupt. This interrupt is issued when the CP tries to open a TxBD,
which is not ready (R = 0). This interrupt is sent only if TxQD[BNM] = 1. The interrupt has
an associated channel code and CID.
Note: The CID number that is placed in the interrupt queue is the one currently located in
the last BD. Because the CID is not updated when the BD is not ready, the CID value is the
one extracted from this BD when it was last processed and transmitted. If the BD is never
processed and the BD was cleared, the CID value could be zero.
Rx buffer interrupt. This interrupt is issued when the I bit is set for an RxBD and the
RxQD[RBM] bit is set. This interrupt has an associated channel code and CID.
Busy condition. The RxBD table associated with this channel's CID is busy. Packets were
discarded due to this condition.
Transmit buffer interrupt. This interrupt is issued when the TxBD[I] bit is set. This interrupt
is sent only if TxQD[TBM] is set. This interrupt has an associated channel code and CID.
Receive SSSAR SDU (frame). An SSSAR frame belonging to this channel's CID has been
received. This interrupt is sent only if RxQD[RFM]=1.
Channel code specifies the ATM channel number associated with this interrupt.
2 3
W 0000_0000
Chapter 33. ATM AAL2
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Description
10
Channel Code (CC)
AAL2 Exceptions
11 12 15
Error_Code
33-41