Motorola PowerQUICC II MPC8280 Series Reference Manual page 1387

Table 40-4 describes the I2CER/I2CMR fields.
Table 40-4. I2CER/I2CMR Field Descriptions
Bits Name
0–2 — Reserved and should be cleared.
3 TXE Tx error. Set when an error occurs during transmission. This event is not maskable via the TxBD[I]
bit.
4 — Reserved and should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two
character times must elapse to guarantee that all data has been sent.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.
40.4.5 I C Command Register (I2COM)
2
The I 2 C command register, shown in Figure 40-10, is used to start I
master or slave mode.
0
Field STR
Reset
R/W
Addr
Figure 40-10. I
Table 40-5 describes I2COM fields.
Bits Name
0 STR Start transmit. In master mode, setting STR causes the I
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I
to load the Tx data register from the I
that matches the slave address with R/W = 1. STR is always read as a 0.
1–6 — Reserved and should be cleared.
7 M/S Master/slave. Configures the I
2
0 I C is a slave.
2
1 I C is a master.
40.5 I C Parameter RAM
2
The I 2 C controller parameter table is used for the general I
the SCC general-purpose parameter RAM. The CP accesses the I
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Freescale Semiconductor, Inc.
1 2 3
2
C Command Register (I2COM)
Table 40-5. I2COM Field Descriptions
2
C Tx buffer and start sending when it receives an address byte
2
C controller to operate as a master or a slave.
Chapter 40. I
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Description
4 5
—
0000_0000
R/W
0x1186C
Description
2
C controller to start sending data from the
2 C parameters and is similar to
2
2
C Controller
2
I C Parameter RAM
2 C transfers and to select
6 7
M/S
2
C controller is idle causes it
C parameter table using
40-9