Motorola PowerQUICC II MPC8280 Series Reference Manual page 1362

Configuring the SPI Controller
MPC8280
Master SPI
The SPISEL
decoder can be
either internal or
external logic.
Figure 39-2. Single-Master/Multi-Slave Configuration
To start exchanging data, the core writes the data to be sent into a buffer, configures a TxBD
with TxBD[R] set, and configures one or more RxBDs. The core then sets SPCOM[STR]
in the SPI command register to start sending data, which starts once the SDMA channel
loads the Tx FIFO with data.
The SPI then generates programmable clock pulses on SPICLK for each character and
simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data
is written into a Rx buffer using the next available RxBD. The SPI keeps sending and
receiving characters until the whole buffer is sent or an error occurs. The CP then clears
TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt controller in the
SIU.
When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting
without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD
is processed after data from the current buffer is sent. Typically there is no delay on
SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current
buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer
is not full; therefore, Rx buffers need not be the same length as Tx buffers.
39-4
Freescale Semiconductor, Inc.
SPIMOSI
SPIMISO
SPICLK
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Slave 0
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 1
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 2
SPIMOSI
SPIMISO
SPICLK
SPISEL
MOTOROLA