Motorola PowerQUICC II MPC8280 Series Reference Manual page 1095

31.10.5.11 AAL1 TxBDs
Figure 31-51 shows the AAL1 TxBD.
0 1
Offset + 0x00 R —
Offset + 0x02
Offset + 0x04
Offset + 0x06
Table 31-39 describes AAL1 TxBD fields.
Offset Bits Name
0x00 0 R
1 —
2 W
3 I
4–5 —
6 CM
7–11 —
0x02 — DL
0x04 — TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
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2 3 4 5
W I — CM
Tx Data Buffer Pointer (TXDBPTR)
Figure 31-51. AAL1 TxBD
Table 31-39. AAL1 TxBD Field Descriptions
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears this bit after the buffer has
been sent or after an error condition is encountered.
1 The buffer prepared for transmission by the user has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
Reserved, should be cleared.
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel's TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table cannot
exceed 64 Kbytes.
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold.
Reserved, should be cleared.
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
Reserved, should be cleared.
The number of octets the ATM controller should transmit from this BD's buffer. It is not
modified by the CP. The value of DL should be greater than zero.
reside in either internal or external memory. This value is not modified by the CP.
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6 7 8 9 10
Data Length (DL)
Description
ATM Memory Structure
11 12 13 14 15
—
31-81