Table 4: Protocols and Applications Supported by ACX Series Routers
Protocol or Application
Building-integrated
timing supply (BITS)
Clock synchronization
Redundant clock
(multiple 1588
primaries)
Transparent clock
ACX1
ACX1
ACX2
ACX2
000
100
000
100
12.2
12.2R
12.2
12.2R
2
2
12.2
12.2R
12.2
12.2R
2
2
–
–
–
–
–
–
–
–
(Continued)
ACX2
ACX4
ACX5
ACX5
200
000
048
096
12.3X
12.3x
–
–
54
51
–D15
-D10
12.3X
12.3x
–
–
54
51
–D15
-D10
–
–
–
–
–
–
15.1X
15.1X
54
54
–D20
–D20
31
ACX5
ACX5
00
448
12.3X
-
54
–D20
(Indoo
r)
12.3X
54
–D25
(Outd
oor)
12.3X
-
54
–D20
(Indoo
r)
12.3X
54
–D25
(Outd
oor)
–
-
–
18.2R
1