Controller Parameters For Intel Stratix 10 Mx Hbm2 Ip - Intel Stratix 10 MX HBM2 IP User Manual

3 Generating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
Display Name
Core clock frequency
Use recommended example design core clock PLL reference
clock frequency
Reference clock frequency for example design core clock
PLL
Related Links
Clock Signals

3.3 Controller Parameters for Intel Stratix 10 MX HBM2 IP

The parameter editor contains one Controller tab for each memory channel that you
specify on the General tab. The Controller tab allows you to select the HBM2
controller options that you want to enable.
Figure 8. Controller Tab
on page 30
Description
select a PLL reference clock frequency from a displayed list.
The values in the list can change when the memory
interface frequency changes or the clock rate of user logic
changes. You should use the fastest possible PLL reference
clock frequency to achieve best jitter performance.
Specifies the clock frequency at which the FPGA core logic
of the AXI4 interface operates. A separate PLL is required to
generate the core clock. The maximum supported core
frequency depends on the device speed grade and timing
closure of this clock within the FPGA. The minimum
frequency of the core clock is one-fourth the HBM2 interface
frequency.
Automatically calculates the example design core clock PLL
reference clock frequency for best performance. Disable this
parameter if you want to select a different reference clock
frequency.
Specify the externally provided reference clock frequency
for the core clock PLL.
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Intel Stratix
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10 MX HBM2 IP User Guide
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