Hbm2 Dram Structure; Intel Stratix 10 Mx Hbm2 Features - Intel Stratix 10 MX HBM2 IP User Manual

1.2 HBM2 DRAM Structure

The HBM DRAM is optimized for high-bandwidth operation to a stack of multiple DRAM
devices across several independent interfaces called channels. Each DRAM stack
supports up to eight channels.
The following figure shows an example stack containing four DRAM dies, each die
supporting two channels. Each die contributes additional capacity and additional
channels to the stack, up to a maximum of eight channels per stack. Each channel
provides access to an independent set of DRAM banks. Requests from one channel
may not access data attached to a different channel.
Figure 2. High Bandwidth Memory Stack of Four DRAM Dies

1.3 Intel Stratix 10 MX HBM2 Features

Intel Stratix 10 MX FPGAs offer the following HBM2 features.
• Supports one to eight HBM2 channels per HBM2 interface in the Pseudo Channel
mode.
• Each HBM2 channel supports a 128-bit DDR data bus, with optional ECC support.
• Pseudo Channel mode divides a channel into two individual 64-bit data interfaces
per channel. The Pseudo Channels share the same Address and Command bus,
but decodes and executes commands individually.
•
Data referenced to strobes
pair per 32 DQs.
•
Differential clock inputs (
interfaces.
® ®
Intel Stratix 10 MX HBM2 IP User Guide
4
1 Introduction to High Bandwidth Memory
/ and
RDQS_t RDQS_c
/ ). Unterminated data/address/cmd/clk
CK_t CK_c
UG-20031 | December 2017
/ , one strobe
WDQS_t WDQS_c