Generating The Example Design - Intel Stratix 10 MX HBM2 IP User Manual

Display Name
Tip: The example design supports generation, simulation, and Intel Quartus Prime
compilation flows for any selected device. To use the example design for simulation,
enable the Simulation parameter. To use the example design for compilation and
hardware, enable the Synthesis parameter.
Table 11. Group: Example Designs / Generated HDL Format
Display Name
Simulation HDL format

3.6 Generating the Example Design

After you finish parameterizing your IP, you can generate the HBM2 example design.
1. On the Example Designs tab, select Simulation/Synthesis in the Example
Design Files group box. (Timing closure is not supported in the 17.1 release.)
2. On the Example Designs tab, select Verilog in the Generated HDL Format
group box.
3. To generate the example design, press the Generate Example Design button, at
the top-right of the parameter editor.
4. When prompted, specify a location at which to save the generated example design
file set.
5. Press OK to begin generating the example design file set.
Upon successful generation of the example design, the system creates file sets to
support both synthesis and simulation of the HBM2 IP. The
hbm_0_example_design/sim/ed_sim
simulators and for the Intel Quartus Prime project.
The generated file hierarchy includes:
• IP - all the generated .ip files, based on the relevant parameters set in the
paramter editor.
• SIM - all the files required to simulate the HBM2 IP for the example design. These
files include the modifiable traffic generator design, the abstract representation of
the hardened HBM2 controller and universal interface block (UIB), and a generic
model of the HBM2 DRAM for simulation.
• qii - includes all the files required to compile the HBM2 IP example design in the
Intel Quartus Prime software version 17.1. Timing closure will be supported in a
future release.
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Intel Stratix 10 MX HBM2 IP User Guide
22
3 Generating the Intel Stratix 10 MX HBM2 IP
Description
the synthesis example design for Platform Designer, and a
file with other corresponding tcl
make_qii_design.tcl
files.
You can run the
make_qii_design.tcl
command line to generate a synthesis example design. The
generated example design resides in the
Description
Specifies the HDL format of the example design file set that
you want to generate.
directory, contains file sets for the supported
UG-20031 | December 2017
file from a
subdirectory.
/qii