Axi Read Transaction - Intel Stratix 10 MX HBM2 IP User Manual

AXI Write Data
During a write burst, the master can assert the
valid write data. Once asserted,
edge after the slave asserts
it is driving the final write transfer in the burst. User logic must issue the write data in
the same order in which the write addresses are issued.
The following diagram illustrates a BL8 Write transaction. The master asserts the Write
address (WA0) in T1 using transaction ID
AWREADY
data in clock cycle T3. Because the controller
data is accepted starting cycle T3. The last piece of the burst 8 transaction is asserted
in clock cycle T6.
Figure 18. AXI Write Transaction
Write Response Channel
The HBM2 controller uses the Write Response channel to respond on successful Write
trasactions. The slave can assert the
response. When asserted,
after the master asserts
the master can always accept a write response in a single cycle.

5.3.2 AXI Read Transaction

® ®
Intel Stratix 10 MX HBM2 IP User Guide
38
WVALID
WREADY
in T2 when the Write command is accepted. The master asserts the Write
BVALID
. The default state of
BREADY
5 Intel Stratix 10 MX HBM2 IP Interface
signal only when it drives
WVALID
must remain asserted until the rising clock
. The master must assert the
, the HBM2 controller asserts the
AWID0
is already asserted, the write
WREADY
signal only when it drives a valid write
BVALID
must remain asserted until the rising clock edge
BREADY
UG-20031 | December 2017
signal while
WLAST
can be high, but only if