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UG-20031 | December 2017
2 Intel Stratix 10 MX HBM2 Architecture
This chapter provides an overview of the Intel Stratix 10 MX HBM2 architecture.
2.1 Intel Stratix 10 MX HBM2 Introduction
Intel Stratix 10 MX devices use the Intel EMIB technology to interface to the HBM2
memory devices.
•
The Intel Stratix 10 MX FPGAs offer up to two HBM2 interfaces.
•
Each HBM2 device can have a device density of 4GB or 8GB, based on the FPGA
chosen.
This system-in-package solution helps to achieve maximum bandwidth and low power
consumption in a small footprint.
2.2 Intel Stratix 10 MX HBM2 Architecture
The Intel Stratix 10 MX device architecture includes the universal interface bus (UIB)
subsystem (UIBSS) which contains the necessary logic to interface the FPGA core to
the HBM2 DRAM.
Each UIB subsystem includes the HBM2 hardened controller and the universal
interface bus, consisting of the hardened physical interface and I/O logic needed to
interface to each HBM2 DRAM device. The AMBA AXI4 protocol interfaces the core
logic with the universal interface bus subsystem. An optional soft logic adapter
implemented in the FPGA fabric helps to efficiently interface user logic to the hardened
HBM2 controller.
The following figure shows a high-level block diagram of the Intel Stratix 10 HBM2
universal interface bus subsystem. The UIB subsystem includes the following
hardened logic:
•
Rate-matching FIFOs that transfer logic from the user core clock to the HBM2
clock domain.
•
HBM2 memory controller (HBMC).
•
UIB PHY, including the UIB physical layer and I/O.
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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