Axi User-Interface Signals - Intel Stratix 10 MX HBM2 IP User Manual

Table 14. Intel Stratix 10 MX Reset Inputs
core_clk_iopll_reset_reset
hbm_0_example_design_wmcrst_n_in_reset_n
hbm_only_reset_in_reset
Related Links
Intel Stratix 10 MX HBM2 IP Example Design for Synthesis

5.2.3 AXI User-interface Signals

The user interface to the HBM2 controller follows the Amba AXI4 protocol
specification. Each AXI port serves the read and write operations for one Pseudo
Channel. Each HBM2 channel consists of two Pseudo Channels, therefore each
controller has two AXI ports.
Each AXI port consists of five sub-channels – read address, write address, write
response, write data and read data; consequently, every HBM2 controller core has ten
AXI subchannels.
The syntax for referencing AXI port signal names is axi_x_y_portname where x is the
channel number and y is the Pseudo Channel number. For example,
refers to the write address ID of the AXI port corresponding to channel 0 and Pseudo
Channel 1.
The signals in the following tables refer to the signal names corresponding to a single
AXI port: Channel 0, Pseudo Channel 0.
Table 15. User Port 0's AXI4 Write Address (Command) Channel
Port Name
axi_0_0_awid
axi_0_0_awaddr
® ®
Intel Stratix 10 MX HBM2 IP User Guide
32
Reset
Width
9 Input
28/29 Input
5 Intel Stratix 10 MX HBM2 IP Interface
Reset input for the core clock I/O PLL. The reset polarity is
active high.
General core logic reset, active low.
HBM-only reset, active high. Not supported in version 17.1.
Direction
Write address ID. This signal is the ID tag for the
write address group of signals.
Write address. The write address gives the
address of the first transfer in a write burst
transaction. This address bus is 28 bits wide for
a 4 GB device and 29 bits for an 8 GB HBM2
device. You must tie the lower-order five bits to
0.
The system derives the address configuration of
the higher-order bits from the following
information. The address ordering that you
choose determines the address configuration of
the higher-order bits:
• Bank address (BA) – 4 bits wide. BA[3:2]
serves as bank group (BG) bits.
• Row address( RA) - 14 bits wide.
• Column address (COL) – 6 bits wide. COL[0]
is tied to 0 for 32B access and COL[1:0] is
tied to 0 for 64B access.
• Stack ID (SID) – 1 bit wide, and applicable
only to 8 GB/8H devices. The controller uses
the SID as a higher order BA bit. The SID is
not available in 4 GB devices.
UG-20031 | December 2017
Description
on page 23
axi_0_1_awid
Description
continued...