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5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
destination asserting the READY signal. Once the source asserts the VALID signal, it
must remain asserted until the handshake occurs, at a rising clock edge at which
VALID and READY are both high. Once the destination asserts READY, it can deassert
READY before the source asserts VALID. The destination can assert READY whenever it
is ready to accept data, or in response to a VALID assertion from the source.
AXI IDs
In an AXI system with multiple masters, the AXI IDs used for the ordering model
include the infrastructure IDs that identify each master uniquely. The ordering model
applies independently to each master in the system.
The AXI ordering model also requires that all transactions with the same ID in the
same direction must provide their responses in the order in which they are issued.
Because the read and write address channels are independent, if an ordering
relationship is required between two transactions with the same ID that are in
different directions, then a master must wait to receive a response to the first
transaction before issuing the second transaction. If a master issues a transaction in
one direction before it has received a response to an earlier transaction in the opposite
direction, there is no ordering guarantee between the two transactions.
AXI Ordering
The AXI system imposes no ordering restrictions between read and write transactions.
Read and write can complete in any order, even if the read address AXI ID (ARID) of a
read transaction is the same as the write address AXI ID (AWID) of a write
transaction. If a master requires a given relationship between a read transaction and a
write transaction, it must ensure that the earlier transaction is completed before it
issues a subsequent transaction. A master can consider the earlier transaction
complete only when one of the following is true:
•
For a read transaction, it receives the last of the read data.
•
For a write transaction, it receives the write response.
5.3.1 AXI Write Transaction
AXI Write Address
You can initiate an AXI write transaction by issuing a valid Write Address signal on the
AXI Write Address Bus. Your user logic should provide the valid write address in the
AWADDR
can assert the
information.
When the HBM2 controller is ready to accept a Write command transaction, it asserts
the
AWREADY
asserted.
bus and assert the
AWVALID
signal only when it drives valid address and control
AWVALID
signal. Address transfer happens when both
to indicate that the address is valid. The master
AWVALID
®
Intel
Stratix
and
are
AWREADY
®
10 MX HBM2 IP User Guide
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