Simulating Intel Stratix 10 Mx Hbm2 Ip With Synopsys Vcs; Simulating Intel Stratix 10 Mx Hbm2 Ip With Riviera-Pro; Simulating Intel Stratix 10 Mx Hbm2 Ip For High Efficiency - Intel Stratix 10 MX HBM2 IP User Manual

4 Simulating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
Save the
do run.do
8. Upon completion of the simulation, the Transcript window displays efficiency data
and other useful information.

4.3 Simulating Intel Stratix 10 MX HBM2 IP with Synopsys VCS*

1. Navigate to the
ed_sim/sim/synopsys/vcs
2. To run the simulation, type
write the output to a log file. The simulation log provides efficiency data and other
useful information.
3. To view the waveform, add
4. To view the waveform, type
necessary signals or module to the waveform view to view the required signals.

4.4 Simulating Intel Stratix 10 MX HBM2 IP with Riviera-PRO*

1. Navigate to:
2. Type
3. Type
4. Type
5. Type

4.5 Simulating Intel Stratix 10 MX HBM2 IP for High Efficiency

The default traffic pattern can achieve high efficiency by efficiently utilizing the HBM2
memory bandwidth and providing an efficient flow of traffic between the HBM2
controller and AXI user interface.
The main steps to deriving higher efficiency are:
• Turn off Enable Reorder Buffer on the Controller tab. The Reorder Buffer
rearranges the read data in the order of the issued requests.
• Turn on Force traffic generator to issue different AXI Read/Write IDs and
Enable Efficiency Test Mode on the Diagnostics tab. In this configuration, the
traffic generator skips the data validation stage based on the different AXI IDs;
consequently, you may receive data mismatch warnings, which you can ignore.
The following sections explain the General, Controller, and Diagnostic tab
parameters required to perform high efficiency HBM2 simulation. The following figures
illustrate parameter settings for a high-efficiency simulation for a single-channel HBM2
controller.
script in the same directory as the
run.do
to run this script from the Transcript window.
project_directory/hbm_0_example_design/sim/
sh vcs_setup.sh
+vcs+dumpvars+test.vcd
project_directory>/sim/ed_sim/aldec
to launch the Riviera-PRO simulator.
rungui
source rivierapro_setup.tcl
to compile the design files and elaborate the top-level design.
ld_debug
to run the HBM2 simulation.
run -all
directory.
. To view the simulation results,
to launch the waveform viewer. Add the
dve &
.
Intel
file. Type
msim_setup.tcl
to the command.
vcs
.
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Stratix 10 MX HBM2 IP User Guide
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