User Axi Interface Timing - Intel Stratix 10 MX HBM2 IP User Manual

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5.3 User AXI Interface Timing

This section explains the interface timing details between user logic and the HBM2
controller. User interface signals follow the AXI4 protocol specification while passing
data to and from the HBM2 controller.
The AXI interface consists of the following channels:
• Write Address channel – Master (user logic) provides relevant signals to issue a
write command to the slave (HBM2 controller).
• Write data channel – Master provides the write data signals corresponding to the
write address.
• Write response channel – Slave provides response on the status of the issued
write command to the master.
• Read Address channel – Master provides relevant signals to issue a read command
to the slave.
• Read data channel – Slave provides read data and read data valid signals
corresponding to the read command to the master.
All transactions in the five channels use a handshake mechanism for the master and
slave to communicate and transfer information.
Handshake Protocol
All five transaction channels use the same VALID/READY handshake process to
transfer address, data, and control information. Both the master and slave can control
the rate at which information moves between master and slave. The source generates
the VALID signal to indicate availability of the address, data, or control information.
The destination generates the READY signal to indicate that it can accept the
information. Transfer occurs only when both the VALID and READY signals are HIGH.
Figure 17. AXI Protocol Handshake Process
In the figure above, the source presents the address, data or control information after
T1 and asserts the VALID signal. The destination asserts the READY signal after T2,
and the source must keep its information stable until the transfer occurs at T3, when
this assertion occurs. In this example, the source asserts the VALID signal prior to the
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Intel Stratix 10 MX HBM2 IP User Guide
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5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
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