Intel Stratix 10 MX HBM2 IP User Manual page 41

6 Intel Stratix 10 MX HBM2 IP Controller Performance
UG-20031 | December 2017
• Write transactions – Refers to user write requests that the HBM2 controller accepts
(user-asserted AXI WVALID and corresponding controller-asserted AXI WREADY).
• Read transactions – Refers to user read requests that the HBM2 controller has
processed (controller-asserted AXI RVALID and corresponding user-asserted AXI
RREADY).
• Total valid transaction count – Accounts for the total time write and read data is
valid across the AXI Interface (WVALID + RVALID)
• Core frequency (MHz) – The frequency at which user logic operates. The core
operates at a lower frequency than the HBM2 interface.
• HBM2 interface frequency (MHz) - The frequency at which the HBM2 interface
operates.
Example: Consider a case where user logic operates at 400 MHz and the HBM2
interface operates at 800 MHz. Assume 7000 accepted write transactions and 7000
accepted read transactions. Total transactions are 8000, with the user logic issuing
concurrent write and read transactions. Efficiency is calculated as follows:
Efficiency = ((7000 + 7000)/8000) * (400/800) * 100 = 87.5%
The HBM2 controller provides high efficiency for any given address pattern from the
user interface. The controller efficiently schedules incoming commands, avoiding
frequent precharge and activate commands as well as frequent bus turn-around when
possible.
Factors Affecting Controller Efficiency
Several factors can affect controller efficiency. For best efficiency, you should consider
these factors in your design:
• User-interface frequency vs HBM2 interface frequency - The frequency of user
logic in the FPGA fabric plays an important role in determining HBM2 memory
efficiency, as shown in the example above.
• Concurrent Write Read Transactions - Both write and read transactions can occur
simultaneously in the AXI interface. Issuing concurrent write and read transactions
can help to maximize utilization of the HBM2 bandwidth.
• Traffic Patterns - Traffic patterns play an important role in determining controller
efficiency. Sequential traffic patterns that make consecutive transactions to the
same open row or page provide higher efficiency, because they avoid frequent
activate and precharge command cycles to the HBM2 memory. You should use the
auto-precharge option with purely random address patterns.
• Burst length - The pseudo-BL8 mode helps to ensure shorter memory access
timing between successive BL4 transactions, to improve controller efficiency.
• AXI Transaction IDs - Efficient use of AXI transaction IDs helps the HBM2
controller schedule the transactions for high efficiency. Use of the same AXI
transaction ID preserves command order.
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Intel Stratix 10 MX HBM2 IP User Guide
41