Intel Stratix 10 Mx Hbm2 Ip Interface; Intel Stratix 10 Mx Hbm2 Ip High Level Block Diagram; Intel Stratix 10 Mx Hbm2 Ip Controller Interface Signals; Clock Signals - Intel Stratix 10 MX HBM2 IP User Manual

UG-20031 | December 2017

5 Intel Stratix 10 MX HBM2 IP Interface

This chapter provides an overview of the signals that interface to the HBM2 IP.

5.1 Intel Stratix 10 MX HBM2 IP High Level Block Diagram

The following figure shows a high-level block diagram of the Intel Stratix 10 MX HBM2
IP. The HBM2 IP communicates with user logic through the AXI protocol.
Figure 16. High Level Block Diagram of HBM2 Implementation

5.2 Intel Stratix 10 MX HBM2 IP Controller Interface Signals

This section lists the signals that connect core logic to the HBM2 IP.

5.2.1 Clock Signals

Each HBM2 interface requires the following
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
clock inputs.
refclk
ISO
9001:2008
Registered