Intel Stratix 10 Mx Hbm2 Ip Latency; Intel Stratix 10 Mx Hbm2 Ip Timing - Intel Stratix 10 MX HBM2 IP User Manual

Table of Contents

6.3 Intel Stratix 10 MX HBM2 IP Latency

Read latency measures the number of clock cycles from the time the HBM2 controller

receives a valid read address command, to the time that valid read data is available at

the user interface.(In other words, from the instant the master asserts the ARVALID

signal and the slave asserts the ARREADY signal, until the slave asserts the RVALID

signal and the master asserts the RREADY signal.)

Read latency includes the controller command path latency to issue the read

command to the HBM2 memory, memory read latency, and the delay in the read data

path through the HBMC memory controller. Simulation reports the minimum latency in

AXI core clock cycles seen during the simulation time.

The maximum HBM2 memory interface frequency is based on the Intel Stratix 10 MX

device speed grade. The maximum core interface frequency is limited by the

frequency at which the core logic can meet timing.

For the best HBM2 efficiency, ensure that your user logic follows best design practices.

Take care to avoid combinatorial paths between the AXI master and slave input and

output signals. Add pipeline registers as necessary and reduce logic levels in timing-

critical paths to successfully meet core timing requirements.

The following documents provide detailed information on the Intel Stratix 10 device

architecture and design techniques that you can adopt to achieve the best core

performance:

•

The Intel Stratix 10 High Performance Design Handbook.

•

The Timing Closure and Optimizations chapter of the Intel Quartus Prime Pro

Edition Handbook Volume 2.