Intel Stratix 10 MX HBM2 IP User Manual page 33

5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Port Name
axi_0_0_awlen
axi_0_0_awsize
axi_0_0_awburst
axi_0_0_awprot
axi_0_0_awqos
axi_0_0_awuser
axi_0_0_awvalid
axi_0_0_awready
Table 16. User Port 0's AXI4 Write Data Channel
Port Name
axi_0_0_wdata
axi_0_0_wstrb
axi_0_0_wuser_data
Width Direction
8 Input
3 Input
2 Input
3 Input
4 Input
1 Input
1 Input
1 Output
Width Direction
128 Input
16 Input
16 Input
Description
Burst Length. The burst length gives the exact
number of transfers in a burst. This information
determines the number of data transfers
associated with the address.
• 0b00000000 = Burst length 1
The AXI interface supports only one burst
transfer at a time, based on burst length 4 or 8.
Burst Size. This signal indicates the size of each
transfer in the burst.
• 0b101 = 32 Bytes
• 0b110 = 64 Bytes
The 32B and 64B access refers to data
corresponding to 64 bits (one Pseudo Channel)
for 4 burst cycles (32B) or 8 burst cycles (64B).
The 64B access granularity is the default for
better efficiency.
Burst Type. The burst type and the size
information, determine how the address for each
transfer within the burst is calculated. This signal
is not supported as multiple bursts are not
supported and only 1 burst is supported at a
time.
Protection Type. [Reserved for Future Use]
This signal indicates the privilege and security
level of the transaction, and whether the
transaction is a data access or an instruction
access.
• 3'b000 = No protection
Quality of Service. The Quality of Service
identifier sent for each write transaction.
• 4'b1111 = High priority
• 4'b0000 = Normal priority
User Signal for auto-precharge.
• 1'b0 = No auto-precharge
• 1'b1 = Auto-precharge
Optional user-defined auto-precharge signal in
the write address channel.
Write Address Valid. Indicates that the channel is
signaling valid write address and control
information.
Write Address Ready. Indicates that the slave is
ready to accept an address and associated
control signals.
Description
Write Data.
Write Strobes (Byte Enables). Indicates which
byte lanes (for u0_wdata) hold valid data. There
is one write strobe bit for every eight bits of
write data.
Extra Write Data (AXI WUSER port). Carries
additional data going to CB bits on HBM2
interface.
® ®
Intel Stratix 10 MX HBM2 IP User Guide
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