Intel iSBC 546 Manuals

Manuals and User Guides for Intel iSBC 546. We have 1 Intel iSBC 546 manual available for free PDF download: Hardware Reference Manual

Intel iSBC 546 Hardware Reference Manual

Intel iSBC 546 Hardware Reference Manual (169 pages)

High Performance Terminal Controllers

Brand: Intel | Category: Controller | Size: 7.03 MB

Table of Contents

Chapter 1 General Information

12
- Table of Contents
  7
Introduction

12
- Board Features
  12
- Board Description
  13
- Isbc 548 Board Description
  13
- Specifications
  19
Chapter 2 Board Operation

22
Introduction

22
- Isbc 547 and Isbc 548 Functional Descriptions
  22
- Isbc 546 Functional Description
  25
Chapter 3 Installation

28
Introduction

28
- Unpacking and Inspection
  28
- Compatible Equipment
  28
- Installation Considerations
  29
- Connector Configurations
  29
Battery Backup

30
Cabling

33
- Pin to Pin Wiring List
  34
- Installation Procedures
  36
Chapter 4 Programmingconsiderations

38
Introduction

38
Jumpers

38
Addressing

38
- Programming Considerations
  38
Firmware

40
- 80186 Processor Programming Considerations
  40
- 8255 Programming
  43
DSR Port

44
Chapter 5 Interfacing Information

46
Introduction

46
Serial Interfaces

51
Chapter 6 Service Assistance Information

58
- Introduction
  58
- Service and Repair Assistance
  58
- Service Diagrams
  60
Appendix Ajumper Information

96
- Introduction
  96
- Jumper Combinations Isbc 547/548 Boards
  98
- Flag Byte Address Jumpers
  99
- Flag Byte Address Options and Jumpers
  99
- MULTIBUS Interrupt Jumpers
  100
- Memory Mapping Jumpers
  100
- Memory Map Jumpers and Addresses
  101
- Isbc
  102
Appendix Bfirmware

106
- Introduction
  106
- Isbc 546, Isbc
  106
- Firmware Operation
  109
- Recommendations for High Performance
  110
- Functional Architecture
  111
- Structures of Dual Ported RAM
  111
- Static Structures
  111
- Dynamic Structures
  111
- Receive Buffers
  111
- Transmit Buffers
  111
  - Layout of Shared (Dual Port) Memory
    111
  - Test Engineering Boot Area Layout
    112
  - Static Structure Area Layout
    114
  - Dynamic Structure Layout
    115
  - Layout of Queue Area
    115
- Inter-Processor Messages
  116
- B.3.2.L Host CPU to Controller Messages
  117
- Initialize
  117
- Conf Igure
  117
  - Initialize Message Format
    117
- Enable Message F0Ril1At
  118
- Disable Message Format
  119
- Transmit Buffer
  125
- Transmit Buffer Message Format
  126
- Abort Transmit Message Format
  127
- Suspend Transmit
  128
- Suspend Transmit Message Format
  128
- Resume Transmit
  129
- Resume Transmit Message Format
  129
- Assert DTR Message Format
  130
- Set CTS and CD Gates Message Format
  131
- Clear CTS and CD Gates Message Format
  132
- Set DSR Report Message Format
  133
- Clear DSR Report Message Format
  134
- Set RI Report Message Format
  135
- Clear RI Report Message Format
  136
- Clear DTR Message Format
  137
- Set Break Message Format
  138
- Clear Break Message Format
  139
- Download Message Format
  142
- Execute Command Message Format
  143
- Clear Receive Buffer Command Message Format
  145
- Transmit Complete Message Format
  146
- Input Available Message Format
  148
- Download Complete Message Format
  149
- Carrier Detect Message Format
  150
- Carrier Loss Message Format
  151
- Initialization Responses Message Format
  152
- Autobaud Complete Message Format
  153
- Special Character Received Message Format
  154
- DSR Detected Message Format
  155
- DSR Lost Message Format
  156
- RI Detected Message Format
  157
- RI Lost Message Format
  158
- EPROM Checksum
  164

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