Intel Stratix 10 MX HBM2 IP User Manual page 16

Table 3. Group: General / FPGA
Display Name
Speed Grade
HBM2 Device Type
HBM2 Location
Table 4. Group: General / HBM2 Interface
Display Name
Add Controller for HBM Channel 0 ––– 7
Table 5. Group: General / AXI Interface
Display Name
Allow backpressure of AXI read data and write response
channels
Threshold temperature for AXI throttling
AXI throttling rate
Table 6. Group: General / Clocks
Display Name
Memory clock interface
Use recommended PLL reference clock frequency
PLL reference clock frequency
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Intel Stratix 10 MX HBM2 IP User Guide
16
3 Generating the Intel Stratix 10 MX HBM2 IP
Description
Specifies the speed grade of the Intel Stratix 10 FPGA.
Select the HBM2 Memory Device: 4GB/4H refers to HBM2
device with a total device density of 4GB in a 4-high Stack,
and 8GB8H refers to a total HBM2 device density of 8GB in
an 8-high Stack.
Selects the location of the HBM2 interface in the Intel
Stratix 10 FPGA.
Description
Allows you to select the HBM2 memory channels that you
want to implement. Each HBM2 channel supports a 128-bit
interface to the HBM2 device, using two 64-bit Pseudo
Channels.
The user interface to the HBM2 Controller uses the AXI4
protocol. Each Controller has one AXI4 interface per Pseudo
Channel or 2 AXI4 interfaces per channel.
Description
Instantiates FIFOs in soft logic to buffer read data and write
response on the AXI interfaces. Enable this parameter if
user logic ever deasserts the AXI
You can disable this parameter to reduce latency, but only if
you never use /
rready bready
interface.
This parameter defines the temperature, in degrees Celsius,
above which the HBM2 controller throttles AXI interface
transactions. The temperature setting applies to all the AXI4
interfaces; however, you must enable this feature on the
corresponding controller tab of each HBM2 controller. When
you enable throttling, the HBM2 controller reduces the
amount of traffic on the DRAM channel.
If you enable AXI interface throttling based on temperature,
this parameter defines the throttle ratio as a percentage (0:
no throttling, 100: full throttling).
Description
Specifies the clock frequency for the HBM2 interface. The
maximum supported HBM2 clock frequency depends on the
FPGA device speed grade:
• -1 Speed grade : 1 GHz
• -2 Speed grade : 800 MHz
• -3 Speed grade : 600 MHz
Automatically calculates the PLL reference clock frequency
for best performance. You should disable this parameter if
you want to select a different PLL reference clock frequency
Enable this parameter only if you disable Use
recommended PLL reference clock frequency, and
want to specify a PLL reference clock frequency. You can
UG-20031 | December 2017
/ signals.
rready bready
to backpressure the
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