Intel Stratix 10 MX HBM2 IP User Manual page 24

Your user logic interfaces to the following signals through the top-level
module:
• Clocks:
— Reference clock input for the UIB PLL that generates the clocks for the UIBSS
and the HBM2 DRA.
— Reference clock input to the I/O PLL that generates the core clock that runs
the user AXI4 interface logic.
• Resets:
—
hbm_0_example_design_pll_ref_clk_clk
—
hbm_0_example_design_wmcrst_n_in_reset_n
—
hbm_only_reset_in_reset
• HBM2 Boundary Scan Signals: The example design requires the boundary scan
signals to be connected for successful compilation, however they are not used.
These do not require to be driven actively or placed in the pin placement file. This
applies to the following signals:
— Input signals:
m2u_bridge_wso[7:0]
— Output signals:
m2u_bridge_wrck
m2u_bridge_updatewr
• Traffic Generator signals: The example design instantiates one traffic generator
per AXI4 interface, or one Pseudo Channel. The traffic generator drives the AXI4
interface signals in the example design. The status signals are provided as outputs
that you can monitor
— AXI4 interface signals: The user logic interfaces to one AXI4 interface per
Pseudo Channel. Each AXI4 interface provides the signals required to interface
to the Write Address, Write Data, Write Response, Read Address and Read
Data Channels.
— User Side Band Advanced Peripheral Bus (APB) Interface: The HBM2 IP
supports one APB interface per HBM2 Channel. The user side band interface is
not supported in 17.1 and will be supported in a future release.
• Traffic Generator status signals:
—
tg<channel num>_<Pseudo Channel
num>_status_traffic_gen_pass
—
tg<channel num>_<Pseudo Channel
num>_status_traffic_gen_fail
—
tg<channel num>_<Pseudo Channel num>_traffic_gen_timeout
Related Links
• Clock Signals
• Reset Signals
• AXI User-interface Signals
® ®
Intel Stratix 10 MX HBM2 IP User Guide
24
(Not currently supported.)
m2u_bridge_cattrip
m2u_bridge_reset_n
,
m2u_bridge_shiftwr
,
m2u_bridge_selectwir and m2u_bridge_wsi
on page 30
on page 31
on page 32
3 Generating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
,
m2u_bridge_temp[2:0]
,
m2u_bridge_wrst_n
,
m2u_bridge_capturewr
ed_synth.v
,
,
,
.