Intel Stratix 10 MX HBM2 IP User Manual page 29

4 Simulating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
to
Set TOP_LEVEL_NAME
To simulate the design, follow the steps in Simulating HBM2 IP with ModelSim.
Synopsys VCS
Navigate to the
ed_sim/sim/synopsys/vcs
and change:
TOP_LEVEL_NAME="ed_sim"
to
TOP_LEVEL_NAME="altera_hbm_tg_axi_tb"
To simulate the design, follow the steps in Simulating HBM2 IP with Synopsys VCS.
Riviera-PRO
Navigate to the
rivierapro_setup.tcl
set TOP_LEVEL_NAME "ed_sim.ed_sim"
to
set TOP_LEVEL_NAME "altera_hbm_tg_axi_171.altera_hbm_tg_axi_tb"
To simulate the design, follow the steps in Simulating HBM2 IP with Riviera-PRO.
"altera_hbm_tg_axi_171.altera_hbm_tg_axi_tb"
project_directory/hbm_0_example_design/sim/
directory. Open the
project_directory/sim/ed_sim/aldec
file in an editor, and change:
file in an editor,
vcs_setup.sh
directory. Open the
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Intel Stratix 10 MX HBM2 IP User Guide
29