Intel Stratix 10 Mx Hbm2 Ip Example Design For Synthesis - Intel Stratix 10 MX HBM2 IP User Manual

3 Generating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
Figure 12. Example Design Hierarchy

3.7 Intel Stratix 10 MX HBM2 IP Example Design for Synthesis

The top level example design for synthesis is available under
hbm_0_example_design/qii/ed_synth/synth/ed_synth.v
ed_synth_hbm_0_example_design
HBM2 IP.
<Design Directory>/
module is the top-level design module for the
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Intel Stratix
. The
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10 MX HBM2 IP User Guide
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