Intel Stratix 10 MX HBM2 IP User Manual page 11

2 Intel Stratix 10 MX HBM2 Architecture
UG-20031 | December 2017
The user interface runs at full rate – that is, data provided on the AXI write or read
data bus on each user clock cycle corresponds to that required in one HBM2 memory
clock cycle.
Command Priority
You can set command priority for a write or read command request through the AXI
interface, through the
address channel. The HBM2 controller supports normal and high priority levels. The
system executes commands with the same priority level in a round-robin scheme.
Starvation limit
The controller tracks how long each command waits and leaves no command
unserviced in the command queue for a long period of time. The controller ensures
that it serves every command efficiently.
Command scheduling
The HBM2 controller schedules the incoming commands to achieve maximum
efficiency at the HBM2 interface. The HBM2 controller also follows the AXI ordering
model of the AXI4 protocol specification.
Data re-ordering
The controller can reorder read data to match the order of the read requests.
Address ordering
The HBM2 controller supports different address ordering schemes that you can select
for best efficiency given your use case. The chosen addressing scheme determines the
order of address configurations in the AXI write and read address buses, including row
address, column address, bank address, and stack ID (applicable only to the 8H
devices). The HBM2 controller remaps the logical address of the command to physical
memory address.
signal in the AXI write address channel, or in the AXI read
qos
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Intel Stratix 10 MX HBM2 IP User Guide
11