Intel i86W Manual page 84

CORE INSTRUCTIONS
II CACHE fLUSH PROCEDURE
II Rw. Rx. Ry. Rz represent integer registers
II fLUSH_P_H is the high-order 16 bits of a pointer to
res~rved
area
II fLUSH_P_L is the low-order 16 bits of the pointer. minus 32
ld.c dirbase. Rz
or 0x800.
Rz.
Rz II RC
<--
0b10 (assuming was 00)
adds -1 r0. Rx II Rx
<--
-1 (loop increment)
call
LfLUSH
st.c
Rz.
dirbase II Replace in block 0
or
0x900.
Rz.
Rz II RB
<--
0b01
call D_fLUSH
st.c
Rz.
dirbase II Replace in block 1
xor 0x900. Rz. Rz II Clear RC and RB
II Change DrB. ATE. or ITI fields here. if necessary
st·c Rz. dirbase
D_fLUSH:
orh
fLUSH_P_H. r0.
Rw II Rw
<--
address minus 32
or fLUSH_P_L. Rw.
Rw
II
of flush area
or
127. r0.
Ry II
Ry
<--
loop count
ld.l
32(Rw) • r31
II
Clear any pending bus writes
shl 0. r31. r31 II Wait until load finishes
bla Rx. Ry. D_fLUSH_LOOP
nop
D_fLUSH_LOOP:
bla Rx. Ry. D_fLH~~_LOOP
flush
bri
ld.l
32(Rw)++
rl
-512(Rw).
r0
II One time to initialize LCC
II Loop; execute next instruction
II for 128 lines in cache block
II flush and autoincrement to next line
II Return after next instruction
II Load from flush area to clear pending
II writes. A hit is guaranteed
Example 5·2. Cache Flush Procedure
5-22