Intel i86W Manual page 135

CHAPTER 7
TRAPS AND INTERRUPTS
Traps are caused by exceptional conditions detected in programs or by external inter-
rupts. Traps cause interruption of normal program flow to execute a special program
known as a trap handler.
7.1 TYPES OF TRAPS
Traps are divided into the types shown in Table 7-1.
7.2
TRAP HANDLER INVOCATION
This section applies to traps other than reset. When a trap occurs, execution of the
current instruction is aborted. The instruction is restartable as described in Section 7.2.3.
The processor takes the following steps while transferring control to the trap handler:
1. Copies U (user mode) of the
psr
into PU (previous U).
2. Copies 1M (interrupt mode) into PIM (previous 1M).
3. Sets U to zero (supervisor mode).
Table 7-1. Types of Traps
Indication Caused by
Type
psr, epsr fsr Condition
Instruction
Instruction
IT
OF Software traps trap, intovr
Fault IL Missing unlock Any
SE Floating-point source exception Any M- or A-unit except fmlow
Floating Floating-point result exception Any M- or A-unit except fmlow, pfgt,
Point FT AO,MO overflow
pfle, and pfeq. Reported on any
Fault AU,MU underflow F-Pinstruction plus pst, fst, and
AI, MI inexact result sometimes fld, pfld, ixfr
Instruction
IAT
Address translation exception Any
Access Fault during instruction fetch
Load/store address translation Any load/store
Data Access
exception
Fault
DAT* Misaligned operand address Any load/store
Operand address matches Any load/store
db register
Interrupt IN External interrupt
Reset No trap bits set Hardware RESET signal
*
These cases can be distinguished
by
examining the operand addresses.
7-1