Intel i86W Manual page 186

PROGRAMMING EXAMPLES
The
faddz
instruction helps to perform the above calculations 64 bits at a time. Because
a Z value is 16 bits wide, Example 9-21 operates on the Z buffer in groups of four. The
faddz
instruction, however, treats the interpolation values (N*mZ) as 32-bit fixed-point
numbers; therefore, two faddz instructions are executed for each group of four pixels.
Because of the way the
faddz
shifts the MERGE register, the first
faddz
corresponds to
even-numbered pixels, while the second corresponds to odd-numbered pixels. Instead of
starting with the value for the first pixel (Z(X1)) and adding mZ to each pixel to produce
the value for the next pixel, the example procedure starts with the values for the first two
even-numbered pixels and adds 1 *mZ to each of these values to produce the values for
the adjacent odd-numbered pair. Adding 3*mZ to each of the Z values of an odd-
numbered pair produces the values for the next even-numbered pair. Figure 9-2 shows
one way of constructing the operands before starting the distance interpolations. (The
initial value given to fsrc1 depends on the alignment of the first pixel.) Table 9-1 helps to
visualize the process.
After two
faddz
instructions, the MERGE register holds the Z values for four adjacent
pixels (in the correct order). The
form
-instruction copies MERGE into one of the 64-bit
floating-point registers. the values
Zl
+
N*mZ. For each execution of
faddz,
src1 is the
same as rdest of the prior
faddz.
After every two
faddz
instructions, a
form
instruction
empties the MERGE register.
The same register is used as both fsrc1 and fdest in all
faddz
instructions. This register
serves to accumulate Z values for successive pixels; therefore, it is called an accumulator.
The registers used as fsrc2 are called interpolants. The code in Example 9-17 constructs
the interpolants; it needs to be executed only once for each polygon.
ACCUMULATOR
63
47
31 15
0
I
Z1 -1.0*mZ
i
FRACTION
I
Z1 - 3.0*mZ
:
FRACTION
I
INITIAL
SRC1
INTERPOLANTS
63
47
31
15 0
3.0*mZ
i
FRACTION
I
3.0*mZ
;
FRACTION
I
FIRST
SRC2
63 47
31
15
0
I
1.0*mZ
!
FRACTION
I
1.0*mZ
FRACTION
I
SECOND
SRC2
240329i
Figure 9-2. faddz Operands
9-24