Intel i86W Manual page 143

TRAPS AND INTERRUPTS
• A memory access is being attempted in violation of the memory protection scheme
defined in Chapter 4.
• A-bit is zero during address translation within a locked sequence.
7.7 INTERRUPT TRAP
An interrupt is an event that is signaled from an external source. If the processor is
executing with interrupts enabled (IM set in the
psr),
the processor sets the interrupt bit
IN in the
psr,
and generates an interrupt trap. Vectored interrupts are implemented by
interrupt controllers and software.
7.8
RESET TRAP
When the i860 microprocessor is reset, execution begins in single-instruction mode at
address OxFFFFFFOO. This is the same address as for other traps. The reset trap can be
distinguished from other traps by the fact that no trap bits are set. The instruction cache
is flushed. The bits DPS, BL, and ATE in
dirbase
are cleared. CS8 is initialized by the
value at the INT pin just before the end of RESET. The read-only fields of the
epsr
are
set to identify the processor, while the IL, WP, PBM, and BE bits are cleared. The bits
U, 1M, BR, and BW in
psr
are cleared. All other bits of
psr
and all other register
contents are undefined. Refer to Table 7-2 for a summary of these initial settings.
The software must ensure that the data cache is flushed (refer to Chapter 4) and control
registers are properly initialized before performing operations that depend on the values
of the cache or registers. The
fir
must be initialized with a
Id.c fir, rO
instruction.
Table 7-2. Register and Cache Values after Reset
Registers Initial Value
Integer Registers Undefined
Floating-Point Registers Undefined
psr
U, 1M, BR, BW
=
0; others
=
undefined
epsr
Il, WP, PBM, BE
=
0; Processor Type, Stepping
Number, DCS are read only; others are undefined
db Undefined
dirbase
DPS, Bl, ATE
=
0
fir
Undefined
fsr
Undefined
KR, KI, MERGE
Undefined
Caches Initial Value
Instruction Cache Flushed
Data Cache Undefined. All modified bits
=
O.
TlB Flushed
7-9