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CORE INSTRUCTIONS
5.1 LOAD INTEGER
Id.x
isrc1 (isrc2), idest
(Load Integer)
idest
+-
mem.x (isrc1
+
isrc2)
.x
=
.b (8 bits),
.S
(16 bits), or .I (32 bits)
The load integer instruction transfers an 8-, 16-, or 32-bit value from memory to the
integer registers. The isrcl can
be
either a 16-bit immediate address offset or an index
register. Loads of 8- or 16-bit values from memory place them in the low-order bits of
the destination registers and sign-extend them to 32-bit values in the destination
registers.
Traps
If
the operand is misaligned, a data-access trap results.
Programming Notes
For best performance, observe the following guidelines:
1. The destination of a load should not be referenced as a source operand by the next
instruction.
2. A load instruction should not directly follow a store that is expected to hit in the
data cache.
Even though immediate address offsets are limited to 16 bits, loads using a 32-bit ad-
dress offset may be implemented by the following sequence
(r31
is recommended for all
such addressing calculations):
orh
HIGH16a, ra, r31
1d.1
LDW16 (r31> ,
ides!
Note that the i860 microprocessor uses signed addition when it adds LOW16 to
r31.
If
bit 15 of LOW16 is set, this has the effect of subtracting from
r31.
Therefore, when bit
15 of LOW16 is set, HIGH16a must be derived by adding one to the high-order 16 bits,
so that the net result is Correct.
The assembler must align the immediate address offsets used in loads to the same
boundary as the effective address, because the lower bits of the immediate offset are
used to encode operand length information.
5-3
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