Intel i960 Series User Manual
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Intel i960 Series User Manual

For cyclone and pci-sdk evaluation platforms
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i960
Microprocessor User Guide
for Cyclone and PCI-SDK
Evaluation Platforms
April 1995
Order Number: 272577-002
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Summary of Contents for Intel i960 Series

  • Page 1 ® i960 Microprocessor User Guide for Cyclone and PCI-SDK Evaluation Platforms April 1995 Order Number: 272577-002...
  • Page 2 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, includin g infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions o f Sale for such products.

  • Page 3: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION ADVANTAGES AND FEATURES ........................1-2 ABOUT THIS MANUAL ..........................1-2 1.2.1 Notation Conventions ..........................1-3 TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS..............1-3 ADDITIONAL INFORMATION ........................1-4 CHAPTER 2 GETTING STARTED PRE-INSTALLATION CONSIDERATIONS ....................2-1 2.1.1 Software Development Tools ........................2-1 2.1.2 MON960 Debug Monitor ...........................
  • Page 4 CONTENTS 3.9.4 CIO Port C .............................. 3-14 3.10 NON-VOLATILE PARAMETER MEMORY....................3-14 3.11 SQUALL II MODULE INTERFACE....................... 3-14 3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)................. 3-16 3.12.1 PCI 9060 Configuration .......................... 3-16 3.12.1.1 Accessing Configuration Registers ....................3-17 3.12.1.2 PCI-to-Local Configuration ......................
  • Page 5 CONTENTS CHAPTER 5 SQUALL II MODULE INTERFACE Physical Attributes ............................5-1 Power Requirements ............................5-3 Squall II Module Serial EEPROM ........................5-3 Squall II Module Signal Definitions ......................... 5-4 Squall Module Signal Descriptions ......................... 5-5 Squall II Module Timing ..........................5-8 5.6.1 Squall II Module Slave Timing ........................
  • Page 6 CONTENTS TABLES Table 3-1 External Connectors and LEDs ......................3-2 Table 3-2 CPU Module Frequency Switch Settings.................... 3-3 Table 3-3 i960 Jx/Hx CPU Clock Rates ......................3-4 Table 3-4 DRAM Access Times.......................... 3-6 Table 3-5 DRAM SIMM Configurations ......................3-7 Table 3-6 Flash ROM Addresses ........................
  • Page 7 CONTENTS...
  • Page 8 CONTENTS viii...
  • Page 9 INDEX...
  • Page 11 INDEX DRAM burst buses 4-6 Bandwidths 3-6 early write cycles 4-6 baud rates features 4-1 on the serial port 3-9 interleaved 3-5 page mode 4-6 performance 3-6 upgrading SIMMs 3-6 Centronics interface 4-5 wait state performance 4-7 chip selects 4-3 DRAM controller 4-8 CIO 3-11 DRAM design...
  • Page 12 INDEX HDIL 2-1 parallel port bit assignments 3-10 Host communications 2-2 control register bit assignments 3-11 Host Debugger Interface Library (HDIL) 2-1 data lines 4-5 handshaking lines 4-5 interrupts 4-5 I/O data buffer control 4-3 timing relationships 4-5 I/O subsystem Parallel Port (Centronics-compatible) 3-2 features 4-1 Parallel port control register 3-10...
  • Page 13 INDEX SIMMs 3-6 types supported 3-6 UART 4-6 Six-position DIP Switch 3-2 Universal Asynchronous Receiver/Transmitter (UART) Software Development Tools 2-1 source-level debuggers 2-1 UNIX support 2-1 Squall 5-2 5-18 Squall II Module, Clock Termination 5-18 Squall II Module, Interrupts 5-3 VPP switch 3-4 Squall II Module, Master Timing 5-12 Vpp Switch 3-4...
  • Page 15 INTRODUCTION...
  • Page 17 Cyclone EP — a standalone general purpose evaluation and development tool. • PCI-SDK Platform — Cyclone EP equipped with a PCI bus interface. Part of Intel’s PCI I/O Software Development Toolkit (SDK). Both platforms allow you to connect one of several i960 CPU and Squall* modules. Using the different CPU modules, you can evaluate the various i960 processors in a system environment, or “benchmark”...

  • Page 18: Introduction

    ABOUT THIS MANUAL This manual contains five chapters, one appendix and an index. A brief description of each follows: Chapter 1, INTRODUCTION Introduces Intel's Cyclone Evaluation Platform and its features. Also defines notation conventions and related documentation. Chapter 2, GETTING...

  • Page 19: Notation Conventions

    TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS For Technical assistance with the Cyclone EP, contact the Intel Technical Support Hotline. For information about technical support in other geographical areas, contact Intel’s North America Technical Support Hotline.

  • Page 20: Additional Information

    INTRODUCTION ADDITIONAL INFORMATION To order manuals from Intel, contact your local sales representative or Intel Literature Sales (1-800-879-4683). Company / Product Document Name Order # ® Intel Solutions960 catalog Intel 270791 ® 80960Cx i960 Cx Microprocessor User's Manual Intel 270710...

  • Page 21: Getting Started

    GETTING STARTED...

  • Page 23: Pre-Installation Considerations

    2.1.2 MON960 Debug Monitor The Cyclone EP is equipped with Intel’s MON960 — an on-board software monitor which allows you to execute and debug programs written for i960 processors. The monitor provides program download, breakpoint, single step, memory display and other useful functions for running and debugging a program.

  • Page 24: Host Communications

    2.1.3.3 Source Level Debugger You may use a source-level debugger, such as Intel’s DB960, GDB960 or other, to establish serial communications with the Cyclone EP. The MON960 Host Debugger Interface Library (HDIL) provides the interface between MON960 and these types of debuggers.

  • Page 25: Software Installation

    GETTING STARTED SOFTWARE INSTALLATION 2.2.1 Installing Software Development Tools If you haven’t done so already, install your development software (CTOOLS960, GNU/960 or other) as described in their respective manuals. All further references to CTOOLS960 or GNU/960 assume the default directories in the respective installation program were selected. You must install the tools before you run the example program as described in Section 2.4, CREATING AND DOWNLOADING THE EXAMPLE PROGRAM.

  • Page 26: Creating And Downloading The Example Program

    GETTING STARTED Power supply connections (not required for the PCI-SDK Platform): the Cyclone EP has two power connectors: J6 and J7. Refer to Section 2.1.4, Power Requirements (pg. 2-2) for a description of these connectors; see Figure 3-1, Cyclone EP and PCI-SDK Platform Physical Diagram (pg. 3-1) to verify locations.
  • Page 27 GETTING STARTED Figure 2-1 shows the messages that display during the download. If using the serial port, the download time increases depending on the baud rate. Section 0, name .text, address 0xA0008000, size 0x6a9c, flags 0x20 writing section at 0xA0008000 Section 1, name .data, address 0xA000ea9c, size 0x4, flags 0x40 writing section at 0xA000ea9c Section 2, name .bss, address 0xA000ea90, size 0x6d0, flags 0x80 -- noload...

  • Page 28: Terminal Emulation-To-Cyclone Ep Communication Support

    GETTING STARTED 2.4.2 Terminal Emulation-to-Cyclone EP Communication Support Invoke the terminal emulation program that you are using to communicate with the Cyclone EP. To establish communication between the terminal emulation program and MON960, press <ENTER>. The MON960 prompt should appear. If it does not, press the RESET button. When the MON960 prompt appears, enter to download: >...

  • Page 29: Hardware Reference

    HARDWARE REFERENCE...

  • Page 31: Connectors, Switches And Leds

    CHAPTER 3 HARDWARE REFERENCE The location of the CPU and Squall modules, connectors, switches, and LEDs are described in this chapter. Also covered are the memory maps, I/O and memory operation. For the PCI-SDK Platform, this chapter describes the PCI 9060 interface and operation.

  • Page 32: Table 3-1 External Connectors And Leds

    HARDWARE REFERENCE Table 3-1. External Connectors and LEDs Function Ref. Description Power +5 VDC A one-pin connector that interfaces to the primary power supply and cable (supplied). Provides +5 VDC and ground connections. (Cyclone EP only) (On the PCI-SDK Platform, power is supplied through the edge connector.) Power +5 VDC, +12 VDC A four-pin connector that interfaces to a secondary power supply and cable (not supplied).

  • Page 33: Cpu Modules

    HARDWARE REFERENCE CPU MODULES As shown in Figure 3-1, a CPU module is a smaller board that attaches directly onto the Cyclone EP. Several CPU modules are available — one for each member of the i960 processor family. Each module contains a i960 processor, boot Flash ROM with the MON960 monitor, appropriate glue logic and configuration switches.

  • Page 34: I960 Jx/Hx Cpu Counter/Timers

    HARDWARE REFERENCE 3.2.3 i960 Jx/Hx CPU Counter/Timers The i960 Jx and Hx processors are equipped with two on-chip counter/timers. These timers are clocked at the CPU clock rate which does not correspond exactly with the CPU Module Frequency Switch settings. Use Table 3-3 to determine the exact CPU clock frequency. Table 3-3.

  • Page 35: Interleaved Dram

    HARDWARE REFERENCE ERRATA (5/95) Figure 3-2, DRAM Memory Map for Cyclone EP, incorrectly showed the PCI Bus Address as 1000 0000H. It now correctly shows 4000 0000H. EFFF FFFFH CPU Module Flash Boot ROM for 80960Cx / Jx / Hx F000 0000H Expansion Flash ROM E000 0000H...

  • Page 36: Upgrading Simm Dram

    HARDWARE REFERENCE Table 3-4. DRAM Access Times Sustained Frequency Operation DRAM Speed Clock Cycles Wait States Bandwidth 16 MHz Read 60, 70ns 3,1,1,1 1,0,0,0 36 Mbytes/sec 20 MHz Read 60, 70ns 3,1,1,1 1,0,0,0 45 Mbytes/sec 25 MHz Read 60ns 3,1,1,1 1,0,0,0 66 Mbytes/sec 25 MHz...

  • Page 37: Flash Memory

    The default configuration of this memory is as the boot memory containing the MON960 monitor. The second bank of memory is two sockets for Intel 28F020 devices (Intel part number N28F020-200) in locations U22 and U27. These memory devices may be used for user application code, or using the SwapROM switch, as boot memory.

  • Page 38: Interrupts

    HARDWARE REFERENCE INTERRUPTS The Cyclone EP has seven interrupt sources. The CPU module assumes the interrupts are direct mapped. Table 3-7 lists the interrupt sources and the corresponding XINT signals. All interrupts are level sensitive except the Squall II Module IRQ0 and IRQ1; these are dependent on the particular Squall II Module installed.

  • Page 39: Console Serial Port

    HARDWARE REFERENCE Table 3-9. 80960Sx and Kx Interrupt Switch Settings Interrupt Source Pos1 Pos2 Pos3 Pos4 Switch Diagram Serial Port UART OFF* OFF* PLX PCI 9060 Squall II Module IRQ1 OFF* PLX PCI 9060 Serial Port UART OFF* Parallel Port O F F Squall II Module IRQ1...

  • Page 40: Parallel Port

    HARDWARE REFERENCE PARALLEL PORT A Centronics PC-compatible receive-only parallel port is implemented on the Cyclone EP. You access and control the parallel port by using three memory-mapped registers (see Table 3-11): • Parallel port data register • Parallel port status register •...

  • Page 41: Z8536 Counter I/O Unit (Cio)

    HARDWARE REFERENCE Table 3-13. Parallel Port Control Register Bit Assignments Signal Mnemonic Signal Name not used — not used — not used — BUSY_CTRL Busy Control PINTEN Enable Interrupt PPOUT Paper Out PPSEL Select Out PPERR Error Output Z8536 COUNTER I/O UNIT (CIO) The Z8536 device performs several functions on the Cyclone EP.

  • Page 42: Cio Port A

    HARDWARE REFERENCE 3.9.2 CIO Port A Port A, an 8-bit input port, is used to report CPU and memory module configuration: • Bits 0-2 report the CPU module processor type. • Bits 3-5 report on the selected CPU module frequency. •...

  • Page 43: Cio Port B

    HARDWARE REFERENCE Table 3-16. CIO Port A Bits 2-0 Module Type CPU Module Type Signals 80960Sx 80960Kx 80960Cx 80960Hx 80960Jx Reserved Reserved Reserved NOTE: 1. Reserved for future processors 3.9.3 CIO Port B Port B is an 8-bit I/O port used to clock, read and write the serial EEPROMs located on the Cyclone EP and the Squall II Module.

  • Page 44: Cio Port C

    HARDWARE REFERENCE 3.9.4 CIO Port C Port C is a 4-bit output-only port used to drive the four User LEDs (CR9) on the Cyclone EP. These LEDs are provided as an aid in debugging. As shown in Figure 3-1, the leftmost LED is LED 0, which corresponds to CIO Port C bit 0;...

  • Page 45: Table 3-17 Available Squall Ii Modules

    HARDWARE REFERENCE Table 3-17. Available Squall II Modules Module Description SQ01 Ethernet (82596CA) SQ10 SCSI-2 (NCR 53C710) SQ11 SCSI-2 Wide (NCR 53C720) SQ20 High Speed Serial with DMA; Two RS-422 (Hitachi 64570) SQ40 Parallel Input with Differential Receivers Table 3-18. Squall Module Compatibility at Maximum CPU Clock Speed (33 MHz) CPU Type SQ01 SQ10...

  • Page 46: Plx Pci 9060 Interface (Pci-Sdk Platform Only)

    HARDWARE REFERENCE 3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only) PLX Technology’s PCI 9060 device provides the PCI-SDK Platform with a PCI bus interface, allowing high-bandwidth data transfer between the PCI-SDK Platform and host or target hardware connected to the PCI bus. The PCI 9060 has several programmable features designed to allow maximum throughput on the PCI bus: •...

  • Page 47: Accessing Configuration Registers

    HARDWARE REFERENCE NOTE: Configure the PCI 9060 for 32-bit i960 Cx CPU mode regardless of the actual CPU module installed. For configuration examples, refer to the MON960 configuration code for the PCI 9060 included with the PCI-SDK Platform. The initial configuration can be divided into the following steps: •...

  • Page 48: Pci-To-Local Configuration

    HARDWARE REFERENCE 3.12.1.2 PCI-to-Local Configuration Before PCI 9060 memory can be accessed through the PCI interface, code on the PCI-SDK Platform must configure the memory regions which will be visible to PCI masters. The PCI 9060 allows one RAM region and one PCI expansion ROM area to be configured as PCI regions. Both of these regions are controlled by the contents of registers in the Local Configuration group (see Table 3-19) which determine region size, location in local memory space, and where it will be mapped in PCI space.

  • Page 49: Ram Region Configuration

    HARDWARE REFERENCE Table 3-20. PCI Configuration Registers Local PCI CFG (Offset from Register chip select Address address) Device ID Vendor ID Status Command Class Code Revision ID BIST Header Type Latency Timer Cache Line Size PCI Base Address for Memory Mapped Runtime Registers PCI Base Address for I/O Mapped Runtime Registers PCI Base Address for Local Address Space 0 Reserved...

  • Page 50: Table 3-21 Memory Region 0 Settings

    HARDWARE REFERENCE Table 3-21. Memory Region 0 Settings Bits Function Setting Bus Width 11 (32 Bit Bus Width) Internal Wait States 0 (No Wait States) READY Input Enable 1 (Enabled) BTERM Input Enable 0 (Disabled) Table 3-22. Local Address Space 0 Range Register Value after Reset Field Description...

  • Page 51: Table 3-24 Local Bus Region Descriptor For Pci-To-Local Access Register Description

    HARDWARE REFERENCE Table 3-24. Local Bus Region Descriptor for PCI-to-Local Access Register Description Value after Reset Field Description Read Write (Cold PC Reset) Memory Space 0 Local Bus Width: 00 indicates a bus width of 8 bits 01 indicates a bus width of 16 bits 10 or 11 indicates a bus width of 32 bits Must be set to 11 (32 bit bus width) Memory Space 0 Internal Wait States.

  • Page 52: Expansion Rom Region Configuration

    HARDWARE REFERENCE 3.12.1.4 Expansion ROM Region Configuration The PCI specification allows expansion boards to include device-specific initialization code in PCI expansion ROM, which is executed at start-up on the host system. Expansion ROM on the PCI-SDK Platform can be configured as a PCI expansion ROM region by programming two Local Configuration registers on the PCI 9060.

  • Page 53: Table 3-26 Local Expansion Rom Local Base Address (Re-Map) And Breqo Register Description

    HARDWARE REFERENCE Local Address Space 0 Local Base Address Register (84H) - A0000001H • The upper 9 bits of this register replace those used to access the local memory from PCI, since 9 bits are set in the Range Register. Bit 0 is set, enabling PCI accesses to this space. Bit 1 is not used and, since this region is mapped into memory space, bits 2 and 3 are also unused.

  • Page 54: Local-To-Pci Configuration

    HARDWARE REFERENCE • A 512 Kbyte space is being mapped, so the lower 19 bits of this register are needed to decode an access. The remaining 13 upper bits are set to 1, so these bits are replaced with the contents of the Local Base Address for PCI-to-Local Expansion ROM (94H).

  • Page 55: Table 3-28 Local Range Register For Direct Master-To-Pci Description

    HARDWARE REFERENCE Local-to-PCI bus options are controlled by settings in the PCI Base Address Register (A8H). Bit 0 must be set (=1) to enable accesses-to-PCI memory space; bit 1 must be set to enable I/O accesses. Bit 2 controls LOCK input from the PCI bus, and should be set. Bit 3 controls pre-fetch size for PCI master accesses, and should be cleared (=0).

  • Page 56: Table 3-30 Local Bus Base Address Register For Direct Master-To-Pci Memory

    HARDWARE REFERENCE MON960 configures a 1 Gbyte region of PCI memory at PCI address 00000000H through 3FFFFFFFH into local memory space at address 40000000H through 7FFFFFFFH. The register settings are: Local Range for Direct Master-to-PCI Register (9CH) - C0000000H • Since 30 bits are needed to encode a 1 Gbyte address space, the lower 30 bits of this register are cleared (=0);...

  • Page 57: Deadlock Configuration

    HARDWARE REFERENCE Table 3-32. PCI Configuration Address Register for Direct Master-to-PCI IO/CFG Value after Reset Field Description Read Write (Cold PC Reset) Configuration Type: 00=Type 0 01=Type 1 Register Number 10:8 Function Number 15:11 Device Number 23:16 Bus Number 30:24 Reserved Configuration Enable.

  • Page 58: Signalling Init Done

    HARDWARE REFERENCE On the Jx processor, an interrupt (XINT3) is asserted. The Kx and Sx processors, however, have no free interrupt lines. As a result, there is no way for these processors to detect the error. The XINT3 interrupt on the Jx processor is intended only to inform the system designer that a deadlock error has occurred, and is a non-recoverable error.

  • Page 59: Local Pci Interrupts

    HARDWARE REFERENCE 3.12.5.1 Local PCI Interrupts Local interrupts from the PCI 9060 are signalled to the i960 processor on XINT0 for Cx, Hx, and Jx processors, and INT2 for the Sx and Kx. Local PCI interrupts may be generated by self-test completion (BIST), either of the DMA channels, the PCI-to-Local Doorbell Register, or LSERR.
  • Page 60 HARDWARE REFERENCE Table 3-33. Interrupt Control/Status (Sheet 2 of 2) Value after Field Description Read Write Reset (Cold PC Reset) Retry Abort Enable: 0 - enable the PCI 9060 to attempt Master Retries indefinitely. 1 - enable the PCI 9060 to treat 256 Master consecutive retries to a Target as a Target Abort.

  • Page 61: Mailbox Registers And Doorbell Interrupts

    HARDWARE REFERENCE 3.12.6 Mailbox Registers and Doorbell Interrupts The PCI 9060 provides eight 32-bit bi-directional mailbox registers and two 32 bit doorbell registers (one PCI-to-i960, one i960-to-PCI). These registers can be used for interprocess communication and synchronization across the PCI bus. Values written to the mailbox registers from one side of the bus can be retrieved by the appropriate process running on the other side.

  • Page 62: Dma Programming

    HARDWARE REFERENCE Triggering a local-to-PCI doorbell interrupt generates a PCI interrupt to the host system. Since a PCI interrupt from the PCI-SDK Platform can be generated by any of several events, the host system should poll the Interrupt Control and Status Register (E8H) on the PCI 9060 to determine the cause of the interrupt.

  • Page 63: Dma Chaining Mode

    HARDWARE REFERENCE PCI Host Memory Set DMA mode to non-chaining Mode Register Memory Block Set up transfer parameters to Transfer PCI Address Register Local Address Register Local Memory Transfer Size (byte count) Register Descriptor Pointer Register (set direction only) Memory Block to Transfer Command/Status Register Setting the Enable and Go bits in the DMA...

  • Page 64: Dma Interrupts

    HARDWARE REFERENCE Example DMA configuration code is included in the PCI-SDK Platform diagnostics, which are packaged with the board. Set DMA mode to chaining PCI Host Memory 1st PCI Address 1st Local Address Mode Register 1st Transfer Size (byte count) 1st Memory Block Set up 1st Descriptor Pointer Register to Transfer...

  • Page 65: Theory Of Operation

    THEORY OF OPERATION...

  • Page 67: Functional Overview

    CHAPTER 4 THEORY OF OPERATION This chapter describes functionality of the Cyclone Evaluation Platform’s subsystems. Section 4.4, I/O INTERFACE describes the general I/O implementation. Subsections further describe each functional block. Section 4.5, DRAM SUBSYSTEM similarly defines the DRAM implementation. Also covered are Clock Generation, Reset, Interrupt and Ready Logic.

  • Page 68: Power Monitor And Reset

    THEORY OF OPERATION POWER MONITOR AND RESET The board reset strobe is provided by a Texas Instruments* TL7705A power supply monitor. The TL7705A senses board voltage and ensures that the board RESET and RESET signals remain asserted for several milliseconds after board power is stable (above 4.6 V). The TL7705A also asserts RESET and RESET when the board voltage drops below 4.6 V.

  • Page 69: Functional Blocks

    THEORY OF OPERATION 4.4.1 Functional Blocks The I/O design comprises four distinct blocks: data path, control logic, registered I/O, and I/O peripheral devices. The schematic for the design is hierarchical. 4.4.2 I/O Control Timing The chip selects and I/O data buffer control are synchronous set-and-hold flip flops in the iFX780 device.

  • Page 70: Data Path

    THEORY OF OPERATION Idle /selflash /selrom /seluart /selpp rd, wr rd, wr rd, wr rd, wr rd, wr rd, wr rd, wr rd, wr, rdyen rd, rdyen, rdy rd, wr rd, wr rd, wr If selcio set ciotrc BLAST rd, wr rd, wr ryden rd, wr...

  • Page 71: Parallel Port

    THEORY OF OPERATION 4.4.3.1 Parallel Port The parallel port is a full implementation of a Centronix-compatible receive-only port. A program sets up and reads the parallel port by reading or writing three registers: Parallel port data register Receives parallel data when the PSTROBE signal is asserted by an external transmit port.

  • Page 72: Serial Port

    THEORY OF OPERATION 4.4.3.2 Serial Port The Cyclone EP provides one RS-232 serial port which is used for communications and program download. This port implements the signals for transmit, receive, clear-to-send and request. Chapter 2, GETTING STARTED contains extensive information on communications and downloading. The serial port interface provides asynchronous RS-232 standard communication for monitors or user- defined applications.

  • Page 73: Bank Interleaving

    THEORY OF OPERATION 4.5.1.1 Bank Interleaving Bank interleaving allows the second, third and fourth accesses of a burst read to occur in zero wait states. The first data access must still pay the entire access penalty. Interleaving significantly improves memory system performance by overlapping accesses to consecutive addresses. Two-way interleaving is accomplished by dividing the memory into two 32-bit banks (also referred to as “leaves”): •...

  • Page 74: Dram Controller Implementation

    4.5.2 DRAM Controller Implementation The DRAM controller — the most complex section of the DRAM design — is implemented by an Intel iFX780 Flex Logic device. The waveforms are controlled by the state machines implemented in the PLDs. This section presents the waveforms and defines these state machines.
  • Page 75 THEORY OF OPERATION /BLAST * PF3 * /W_R Precharge Precharge Assert /REF /REPEND /BLAST * PF0 Precharge/Idle Assert /REF /ADS * seldram *(PF1 + PF2 + PF3) Assert /REF. /RAS Assert RAS* Assert RAS* Assert CASEN* If /(PF3 * /W_R) Assert /REF.

  • Page 76: Cas Generation

    THEORY OF OPERATION CAS Generation The CAS signals to the A and B banks of DRAM are generated from a high speed 20V8 PAL with clock to output timing of 5 ns. The BANKSEL signal from the iFX780 determines which set of CAS signals is asserted.

  • Page 77: Squall Ii Module Interface

    SQUALL II MODULE INTERFACE...

  • Page 79: Physical Attributes

    CHAPTER 5 SQUALL II MODULE INTERFACE Design information, electrical and physical specifications of the Squall II Module interface are described in this chapter. This information is useful when you wish to design and integrate your own Squall Modules. If you are using a standard Squall Module, refer to the specific module's manual for information on the operation of that module.
  • Page 80 SQUALL II MODULE INTERFACE 3.650” 0.850” 100-Pin Connector Samtec TFM-150-32-SDLC all three holes are 0.120” DIA. thru Pin 100 Pin 50 Pin 51 123-1234-12 Rev. xxxx Pin 1 CYCLONE MICROSYSTEMS COPYRIGHT 1995 0.850” 3.535” 3.850” NOTE: Dimensions of J1 placement are to center line of the component in x axis and center line of pins 1 and 51 in y axis.

  • Page 81: Power Requirements

    SQUALL II MODULE INTERFACE Power Requirements The Squall II Module connectors supply +5v and +12v. Make sure you do not exceed the maximum amperage listed in Table 5-1. If power is lead off the module via the front panel or the J6/P2 connector, a fuse should be used to prevent damage to the Cyclone EP that may occur due to an incorrect connection.

  • Page 82: Squall Ii Module Signal Definitions

    SQUALL II MODULE INTERFACE As with on-board EEPROM, bytes are read from and written to the 24C08 EEPROM most significant bit (bit 7) first and least significant bit (bit 0) last. ADDRESS DESCRIPTION 7FFH Module-specific data (see the particular module’s user manual) 00AH 009H Module revision level...

  • Page 83: Squall Module Signal Descriptions

    SQUALL II MODULE INTERFACE Table 5-2. Pin Description Nomenclature Symbol Description Input only pin Output only pin Pin may be either an input or output Pin must be connected as described Synchronous. Inputs are synchronous to PMCLK. Outputs must meet setup and hold times relative to PMCLK.
  • Page 84 SQUALL II MODULE INTERFACE Table 5-3. Squall Module Signal Descriptions (Sheet 2 of 3) Name Type Description S_BE3 SL(I) Byte Enables select which of the four bytes addressed by A[02:31] are active during an access to a memory region configured as 32 bits data bus width. The S_BE2 M(O) following describes the usage of the Byte Enable Signals in different data bus...
  • Page 85 SQUALL II MODULE INTERFACE Table 5-3. Squall Module Signal Descriptions (Sheet 3 of 3) Name Type Description S_BLAST SL(I) Burst Last indicates the last transfer in a bus access. In slave mode S_BLAST is asserted in the data transfer of burst and non-burst accesses after the processor’s M(O) wait state counter reaches zero.

  • Page 86: Squall Ii Module Timing

    SQUALL II MODULE INTERFACE Squall II Module Timing The Squall Interface signals are an enhanced set of the i960 Cx processor’s bus signals. The interface has two modes of operation: slave and master. • In slave mode the processor is accessing devices on the Squall II Module. •...

  • Page 87: Table 5-4 Squall Ii Module Slave Timing

    Clock to Output, S_DATA (Write) NOTE: Signal timing is dependent on the type of i960 processor and the frequency of operation. Refer to Intel i960 pr o- cessor data sheets for this timing information . Figure 5-5, Squall II Slave Burst Read Timing Diagram shows 3,1,1,1 clock cycle read; Figure 5-6, Squall II Slave Burst Write Timing Diagram shows 3,2,2,2 clock cycle write.
  • Page 88 SQUALL II MODULE INTERFACE D600A PMCLK S_ADS SQxSEL S_BLAST S_ADDR S_BEx S_W/R S_DATA t9 t10 t9 t10 S_READY NOTE: Diagram shows two wait states; any number of wait states are acceptable. Figure 5-4. Squall II Slave Read and Write Timing Diagram 5-10...
  • Page 89 SQUALL II MODULE INTERFACE PMCLK S_ADS SQxSEL S_BLAST S_A[4:31] S_A[2:3] S_W/R t4 t5 t4 t5 t4 t5 S_DATA S_READY Figure 5-5. Squall II Slave Burst Read Timing Diagram 5-11...

  • Page 90: Squall Ii Module Master Timing

    SQUALL II MODULE INTERFACE PMCLK S_ADS SQxSEL S_BLAST S_A[4:31] S_A[2:3] S_W/R S_DATA S_READY Figure 5-6. Squall II Slave Burst Write Timing Diagram 5.6.2 Squall II Module Master Timing Squall II Module circuits may become masters of the shared bus to perform DMA operations to the shared DRAM.

  • Page 91: Table 5-5 Squall Ii Module Master Timing

    SQUALL II MODULE INTERFACE The optional use of the EXTEND signal has been added to the interface to facilitate interfacing slower, older DMA controller designs. EXTEND may only be used in single transfer read cycles to extend the time valid data is on the data bus. During an access with EXTEND asserted, the DRAM controller presents valid data on the bus with READY asserted.
  • Page 92 SQUALL II MODULE INTERFACE B610.TD PMCLK SQBR SQBG S_ADS S_BLAST S_EXTEND S_ADDR S_W/R S_DATA S_READY Figure 5-7. Squall II Master Read and Write Timing Diagram 5-14...
  • Page 93 SQUALL II MODULE INTERFACE D612A.TD PMCLK SQBR SQBG S_ADS S_BLAST S_EXTEND S_ADDR S_W/R S_DATA S_READY Figure 5-8. Squall II Master Burst Read and Write Timing Diagram Figure 5-9, Squall II Master Read Using S_EXTEND, shows a three clock cycle access. Refresh cycles may cause READY to be delayed by up to 10 additional clock cycles.
  • Page 94 SQUALL II MODULE INTERFACE D611A.TD PMCLK SQBR SQBG S_ADS S_BLAST S_EXTEND S_ADDR S_BEx S_W/R S_DATA S_READY Figure 5-9. Squall II Master Read Using S_EXTEND 5-16...

  • Page 95: Squall Ii Module Connector

    SQUALL II MODULE INTERFACE Squall II Module Connector The Squall II Module interface uses a 100-pin surface mount connector plug. Samtec* part number for the connector is TFM-150-32-SDLC. Table 5-6 shows pin assignments for the Squall II Module connector. Table 5-6. Squall II Module Pin Assignments Signal Signal Signal...

  • Page 96: Squall Ii Module Signal Loading And Logic Selection

    SQUALL II MODULE INTERFACE Squall II Module Signal Loading and Logic Selection Selection of logic families for Squall II Modules deals mostly with the edge rate of the outputs. CMOS logic families, although they use less power than their bipolar predecessors, can be very noisy due to very fast edges transitioning full 5 volt swings from rail to rail.

  • Page 97: Parts List

    PARTS LIST...

  • Page 99: Table A-1 Cyclone Ep/Pci-Sdk Platform Bill Of Materials

    Manufacturer Central Diode CMSH1-20 Semiconductor Texas UART TL16C550AFN Instruments Memory EPROM X24C08S8 Xicor U22, U27 Non-Volatile Memory N28F020-200 Intel U12, U21, U25, U26 74ABT241D National Texas SN74ABT245DW Instruments U2, U3 Texas SN74ABT574DW Instruments U1, U4, U5 Texas SN74LS244DW Instruments Clock Chip...
  • Page 100 CR1, CR2, CR3, Green LED LTL533-11 Lite-On CR4, CR5 Red LED LTL503-11 Lite-On Red LED Package 555-4001 Dialight MAX233ACWP Maxium MAX767CAP Maxium MAX8215CSD Maxium PALCE20V8H-7JC Intel PAL22V10-15JC Intel PCI to 80960 Chip PCI9060 PLX Technology Resistor, 1/8W, 1K, 5% BCRY8102JT Beckman...
  • Page 101 Resistor Package, 1K 4816P-T02-102 Bourns Resistor Package, 4.7K 4816P-T02-472 Bourns DIP Switch DHS-45 Mors-Asc Push Button Switch EP12-D1A-BE C&K Texas TL7705ACD Instruments Crystal KDS143-20 KDS America Z0853606VSC Zilog FPGA iFX780-84-10 Intel N85C220-10 Intel Resistor, 1/8 W, 2.2K, 5% BCRY8222JT Beckman...
  • Page 102 PARTS LIST...

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