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CORE INSTRUCTIONS
5.5 STORE FLOATING-POINT
fst.y fdest, isrc1(isrc2)
fst.y fdest, isrc1(isrc2)
+ +
mem.y (isrc2
+
isrc1)
~
fdest
IF autoincrement
THEN isrc2
~
isrc1
+
isrc2
FI
Floating-Point Store
(Normal)
(Autoincrement)
.y
=
.I
(32 bits), .d (64 bits), or
.q
(128 bits)
Floating-point stores transfer 32-, 64-, or 128-bit values from the floating-point registers
to memory. These may be floating-point values or integers. Floating-point stores allow
isrcl to be used as an index register. An autoincrement option supports constant-stride
vector addressing.
If
this option is specified, the i860 microprocessor stores the effective
address into isrc2.
Traps
If
the operand is misaligned, a data-access trap results.
Programming Notes
For the auto incrementing form of the instruction, the register coded as isrcl must not be
the same register as isrc2.
For best performance, observe the following guidelines:
1. A
fld
instruction should not directly follow a store instruction that is expected to hit .
in the data cache. There is no performance impact for a
pfld
following a store
instruction.
,2. The fdest of an
fst.y
instruction should not reference the destination of the next
instruction if that instruction is a pipelined floating-point operation.
The assembler must align the immediate address offsets used in stores to the same
boundary as the effective address, because the lower bits of the immediate offset are
used to encode operand length information.
5-8
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