Table of Contents
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TABLE OF CONTENTS
APPENDIX A
INSTRUCTION SET SUMMARY
APPENDIX B
INSTRUCTION FORMAT AND ENCODING
APPENDIX C
INSTRUCTION TIMINGS
APPENDIX D
INSTRUCTION CHARACTERISTICS
Figures
Figure
Title
Page
1-1
Registers and Data Paths ...............................................................................
1-2
2-1
Pixel Format Examples ...................................................................................
2-4
3-1
Register Set ....................................................................................................
3-1
3-2
Processor Status Register ............................................................................ ..
3-3
Extended Processor Status Register .............................................................
3-5
3-4
Directory Base Register ..................................................................................
3-6
3-5
Floating-Point Status Register ........................................................................
3-9
4-1
Memory Formats .............................................................................................
4-1
4-2
Big and Little Endian Memory Transfers .......... .................... ..........................
4-2
4-3
Format of a Virtual Address ............................................................................
4-3
4-4
Address Translation ........................................................................................
4-4
4-5
Format of a Page Table Entry ........................................................................
4-5
4-6
Invalid Page Table Entry .................................................. .......... ........ ............
4-5
6-1
Pipelined Instruction Execution ........ .............................................. ........... .....
6-3
6-2
Dual-Operation Data Paths .............................................................................
6-16
6-3
Data Paths by Instruction (1 of 8) ........................ ..........................................
6-18
6-4
Data Path Mnemonics ................................... .................................................
6-26
6-5
PSR Fields for Graphics Operations ........................ ......................................
6-29
6-6
FADDP with 8-Bit Pixels ..................................................................................
6-33
6-7
FADDP with 16-Bit Pixels ................................................................................
6-34
6-8
FADDP with 32-Bit Pixels ................................................................................
6-35
6-9
FADDZ with 16-Bit Z-Buffer ................................... .................................. .......
6-36
6-10
64-Bit Distance Interpolation ..........................................................................
6-37
6-11
Dual-Instruction Mode Transitions (1 of 2) .............................................. .......
6-40
8-1
Register Allocation ..........................................................................................
8-2
8-2
Stack Frame Format .......................................................................................
8-6
8-3
Example Memory Layout ................................................................................
8-7
9-1
Z-Buffer Interpolation ......... .................................... .............. ...........................
9-23
9-2
faddz
Operands .............................................................................................
9-24
9-3
Pixel Interpolation for Gouraud Shading ........................................................
9-27
9-4
faddp
Operands .............................................................................................
9-27
x
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