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TRAPS AND INTERRUPTS
4. Sets 1M to zero (interrupts disabled). This guards against further interrupts until the
trap information can be saved.
5. If the processor is in dual instruction mode, it sets DIM; otherwise DIM is cleared.
6. If the processor is in single-instruction mode and the next instruction will be exe-
cuted in dual-instruction mode or if the processor is in dual-instruction mode and
the next instruction will be executed in single-instruction mode, DS is set; otherwise,
it is cleared.
7. The appropriate trap type bits in
psr
and
epsr
are set (IT, IN, IAT, DAT, FT, IL).
Several bits may be set if the corresponding trap conditions occur simultaneously.
8. An address is placed in the fault instruction register
(fir)
to help locate the trapped
instruction. In single-instruction mode, the address in
fir
is the address of the
trapped instruction itself. In dual-instruction mode, the address in
fir
is that of the
floating-point half of the dual instruction. If an instruction- or data-access fault
occurred, the associated core instruction is the high-order half of the dual instruc-
tion
(fir
+
4). In dual-instruction mode, when a data-access fault occurs in the
absence of other trap conditions, the floating-point half of the dual instruction will
already have been executed.
9. Clears the BL bit of
dirbase
and deasserts LOCK#.
The processor begins executing the trap handler by transferring execution to virtual
address OxFFFFFFOO. The trap handler begins execution in single-instruction mode. The
trap handler must examine the trap-type bits in
psr
(IT, IN, IAT, DAT, FT) and
epsr
(IL, OF) to determine the cause or causes of the trap.
7.2.1 Saving State
To support nesting of traps, the trap handler must save the current state before another
trap occurs. An interrupt stack can be implemented in software (refer to the section on
stack implementation in Chapter 8). Interrupts can then be reenabled by clearing the
trap-type bits and setting 1M to the value of PIM. Further, the trap handler must ensure
that no trap may occur once the restoration of the initial state (described in Section
7.2.3) has begun prior to returning from the trap handler. The branch-indirect instruc-
tion is sensitive to the trap-type bits; therefore, clearing the trap-type bits allows normal
indirect branches to be performed within the trap handler.
The items that make up the current state may include any of the following:
1. The
fir.
2. The
psr.
3. The
epsr.
7-2
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