Dual-Instruction Mode Transitions (1 Of 2) - Intel i86W Manual

FLOATING-POINT INSTRUCTIONS
6.8 DUAL-INSTRUCTION MODE
The i860 microprocessor can execute a floating-point and a core instruction in parallel.
Such parallel execution is called dual-instruction mode. When executing in dual-
instruction mode, the instruction sequence consists of 64-bit aligned instructions with a
floating-point instruction in the lower 32 bits and a core instruction in the upper 32 bits.
Programmers specify dual-instruction mode either by including in the mnemonic of a
floating-point instruction a
d.
prefix or by using the Assembler directives
.dual '" .end-
dual.
Both of the specifications cause the D-bit of floating-point instructions to be set. If
the i860 microprocessor is executing in single-instruction mode and encounters a
floating-point instruction with the D-bit set, one more 32-bit instruction is executed
before dual-mode execution begins.
If
the i860 microprocessor is executing in dual-
instruction mode and a floating-point instruction is encountered with a clear D-bit, then
one more pair of instructions is executed before resuming single-instruction mode.
Figure 6-11 illustrates two variations of this sequence of events: one for extended
sequences of dual-instructions and one for a single instruction pair.
When a 64-bit dual-instruction pair sequentially follows a delayed branch instruction in
dual-instruction mode, both 32-bit instructions are executed.
63
31
op
d. fp-op
d. fp-op or core-op
cgr~~
d. fp-op
core-op
fp-op
core-op
fp-op
op
op
o
Enter Dual Instruction Mode.
Initiate Exit from
Dual-Instruction Mode.
1
.Leave
Dual-Instruction Mode.
1
240329i
Figure 6-11. Dual-Instruction ModeTransitions (1 of 2)
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