Intel i86W Manual page 203

INSTRUCTION SET SUMMARY
fzchkl
fsrcl, fsrc2, fdest ........................................................................ 32-Bit Z-ButTer Check
Consider fsrcl, fsrc2, and fdest as arrays of two 32-bit
fields fsrcl (O)./srcl (1), fsrc2 (O)./src2 (1), and fdest (O)./dest (1)
where zero denotes the least-significant field.
PM
~
PM shifted right by 2 bits
FOR i
=
0 to 1
DO
PM [i
+
6]
~
fsrc2(i)
:5
fsrcl(i) (unsigned)
fdest(i)
~
smaller of fsrc2(i) and fsrcl (i)
OD
MERGE~O
fzchks fsrcl, fsrc2, fdest ....................................................................... 16-Bit Z-ButTer Check
Consider fsrcl, fsrc2, and fdest as arrays of four 16-bit
fields fsrcl (O)./srcl (3), fsrc2(O)./src2(3), and fdest(O)./dest(3)
where zero denotes the least-significant field.
PM ~ PM shifted right by 4 bits
FOR i
=
0 to 3
DO
PM [i
+
4]
~
fsrc2(i)
:5
fsrcl(i) (unsigned)
fdest(i)
~
smaller of fsrc2(i) and fsrcl(i)
aD
MERGE~O
intoYr ...............................................................................
Software Trap on Integer Overflow
IF OF
=
1
THEN generate trap with IT set in
psr
FI
ixfr
isrclni, fdest ................................................................... Transfer Integer
to
F-P Register
fdest
~
isrclni
Id.c
csrc2, idest ............................................................................ Load from Control Register
idest
~
csrc2
Id.x isrcl (isrc2) , idest ............................................................................................ Load Integer
idest
~
mem.x (isrcl
+
isrc2)
lock ..............................................................................................
Begin Interlocked Sequence
Set
BL
in
dirbase.
The next load or store that misses the cache locks that location.
Disable interrupts until the bus is unlocked.
moy
isrc2, idest ................................................................................... Register-Register Move
Assembler pseudo-operation
moy isrc2, idest
=
shl rO, isrc2, idest
A-7