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INSTRUCTION CHARACTERISTICS
6. The destination should not be a source operand of the next instruction.
7. When the prior operation is scalar and multiplier opi is fsrei, fsre2 should not be
the same as the fdest of the prior operation.
8. When the prior operation is scalar, srei and sre2 of the current operation should
not be the same as dest of the prior operation.
9. A
pfld
should not immediately follow a
pfld
• Programming restrictions. These indicate combinations of conditions that must be
avoided by programmers, assemblers, and compilers. The following notes define the
alphabetic codes that appear in the instruction table:
a. The sequential instruction following a delayed control-transfer instruction may not
be another control-transfer instruction, nor a
trap
instruction, nor the target of a
control-transfer instruction.
b. When using a
bri
to return from a trap handler, programmers should take care to
prevent traps from occurring on that or on the next sequential instruction. 1M
should be zero (interrupts disabled) when the
bri
is executed.
c. If dest is not zero, fsrei must not be the same as dest.
d. When fsrei goes to multiplier opi or to KR or KI, fsrei must not be the same as
rdest.
e. If dest is not zero, srei and sre2 must not be the same as dest.
f. Isrei
must not be the same register as isre2 for the autoincrementing form of this
instruction.
Instruction
Execution
Pipelined?
Sets
Faults
Performance
Programming
Unit
Delayed?
CC?
Notes
Restrictions
adds
E
CC
1
addu
E
CC
1
and
E
CC
andh
E
CC
andnot
E
CC
andnoth
E
CC
bc
E
bC.t
E
0
a
bla
E
0
a, f
bnc
E
bnc.t
E
0
a
br
E
0
a
bri
E
0
a, b
bte
E
btne
E
call
E
0
6
a
calli
E
0
6
a
fadd.p
A
SE,RE
0-2
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