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CORE INSTRUCTIONS
5.2
STORE INTEGER
st.x isrc 1 ni, #const (isrc2)
(Store Integer)
mem.x (isrc2
+
#const)
~
isrc1 ni
.X =
.b (8 bits),
.S
(16 bits), or
.I
(32 bits)
The store instruction transfers an 8-, 16-, or 32-bit value from the integer registers to
memory. Stores do not allow an index register in the effective-address calculation, be-
cause isrclni is used to specify the register to be stored. The #const is a signed, 16-bit,
immediate address offset. An absolute address may be formed by using the zero register
for isrc2. Stores of 8- or 16-bit values store the low-order 8 or 16 bits of the register.
Traps
If
the operand is misaligned, a data-access trap results.
Programming Notes
For best performance, a load instruction should not directly follow a store that is ex-
pected to hit in the data cache.
Even though immediate address offsets are limited to 16 bits, a store using a 32-bit
immediate address offset may be implemented by the following sequence
(r31
is recom-
mended for all such addressing calculations):
orh
HIGH16a, r0, r31
st.
1
isrc 1 ni,
LOW
16 ( r 31>
Note that the i860 microprocessor uses signed addition when it adds LOW16 to
r31.
If
bit 15 of LOW16 is set, this has the effect of subtracting from
r31.
Therefore, when bit
15 of LOW16 is set, HIGH16a must be derived by adding one to the high-order 16 bits,
so that the net result is correct.
The assembler must align the immediate address offsets used in stores to the same
boundary as the effective address, because the lower bits of the immediate offset are
used to encode operand length information.
5-4
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