Intel i86W Manual page 90

FLOATING-POINT INSTRUCTIONS
Table 6-1. Precision Specification
Suffix
Source Precision
Result Precision
.ss single single
.sd single double
.dd
double double
.ds
double single
6.2 PIPELINED AND SCALAR OPERATIONS
The architecture of the floating-point unit uses parallelism to increase the rate at which
operations may be introduced into the unit. One type of parallelism used is called "pipe-
lining." The pipelined architecture treats each operation as a series of more primitive
operations (called "stages") that can be executed in parallel. Consider just the floating-
point adder unit as an example. Let A represent the operation of the adder. Let the
stages be represented by AI' Az, and A
3 •
The stages are designed such that Ai
+
I for one
adder instruction can execute in parallel with Ai for the next adder instruction. Further-
more, each Ai can be executed in just one clock. The pipelining within the multiplier and
graphics units can be described similarly, except that the number of stages and the
number of clocks per stage may be different.
Figure 6-1 illustrates three-stage pipelining as found in the floating-point adder (also in
the floating-point multiplier when single-precision input operands are employed). The
columns of the figure represent the three stages of the pipeline. Each stage holds inter-
mediate results and also (when introduced into the first stage by software) holds status
information pertaining to those results. The figure assumes that the instruction stream
consists of a series of consecutive floating-point instructions, all of one type (i.e. all
adder instructions or all single-precision multiplier instructions). The instructions are
represented as i, i
+
1, etc. The rows of the figure represent the states of the unit at
successive clock cycles. Each time a pipelined operation is performed, the status of the
last stage becomes available in
fsr,
the result of the last stage of the pipeline is stored in
the destination register fdest, the pipeiine is advanced one stage, and the input operands
fsrcl and fsrc2 are transferred to the first stage of the pipeline.
In the i860 microprocessor, the number of pipeline stages ranges from one to three. A
pipelined instruction with a three-stage pipeline writes to its fdest the result of the third
prior instruction. A pipe lined instruction with a two-stage pipeline writes to its fdest the
result of the second prior operation. A pipelined operation with a one-stage pipeline
stores the result of the prior operation. '
There are four floating-point pipelines: one for the multiplier, one for the adder, one for
the graphics unit, and one for floating-point loads. The adder pipeline has three stages.
The number of stages in the multiplier pipeline depends on the precision of the source
operands in the pipeline: two stages for double precision or three stages for single pre-
cision. The graphics unit has one stage for all precisions. The load pipeline has three
stages for all precisions.
6-2