Intel i86W Manual page 85

CORE INSTRUCTIONS
5.14 BUS LOCK
lock (Begin interlocked sequence)
Set BL in dirbase. The next load or store that misses the cache
locks that location, preventing locked access to it by other processors.
External interrupts are disabled from the first
instruction after the lock until the location is unlocked.
unlock (End interlocked sequence)
Clear BL in dirbase. The next load or store unlocks the location
(regardless of whether it hits in the cache). Interrupts are enabled.
These instructions allow programs running in either user or supervisor mode to perform
read-modify-write sequences in multiprocessor and multithread systems. The interlocked
sequence must not branch outside of the 30 sequential instructions following the
lock
instruction. The sequence must be restartable from the lock instruction in case a trap
occurs. Simple read-modify-write sequences are automatically restartable. For sequences
with more than one store, the software must ensure that no traps occur after the first
non-reexecutable store. To ensure that no data access fault occurs, it must first store
unmodified values in the other store locations. To ensure that no instruction-access fault
. occurs, the code that is not restartable should not span a page boundary.
After a
lock
instruction, the location is not locked until the first data access that misses
the data cache. Software in a multiprocessing system should ensure that the first load
instruction after a
lock
references noncacheable memory.
If a trap occurs after a
lock
instruction but before the load or store that follows the
corresponding unlock, the processor clears BL and sets the IL (interlock) bit of epsr.
This is likely to happen, for example, during TLB miss processing, when the A-bit of the
page table entry is not set.
If the processor encounters another lock instruction before unlocking the bus or an
unlock
with no preceeding
lock,
that instruction is ignored.
If, following a
lock
instruction, the processor does not encounter a load or store follow-
ing an
unlock
instruction by the time it has executed 30-33 instructions, it triggers an
instruction fault. In such a case, the trap handler will find both IL and IT set. The
instruction pointed to by fir mayor may not have been executed.
When multiple memory locations are accessed during a locked sequence, only the first
location with a cache miss is guaranteed to be locked against access by other processors.
For high-performance multiprocessors, this allows a read-for-ownership policy, instead
of locking the system bus.
Between locked sequences, at least one cycle of LOCK# deactivation is guaranteed by
the behavior of
unlock.
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