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5.13
CACHE FLUSH
flush #const(isrc2)
flush #const(isrc2)
+ +
CORE INSTRUCTIONS
(Cache flush)
(Normal)
(Autoincrement)
Replace the block in data cache that has address (#const
+
isrc2).
Contents of block undefined.
IF autoincrement
THEN isrc2
~
#const
+
isrc2
FI
The
flush
instruction is used to force modified data in the data cache to external mem-
ory. Because the register designated by idest is undefined after
flush,
assemblers should
encode idest as zero. The address #const
+
isrc2 must be aligned on a 16-byte boundary.
There are two 32-byte blocks in the cache which can be replaced by the address #const
+
isrc2. The particular block that is forced to memory is controlled by the RB field of
dirbase.
In user mode, execution of
flush
is suppressed; use it only in supervisor mode.
Example 5-2 shows how to use the
flush
instruction. The addresses used by the
flush
instruction refer to a reserved 4 Kbytc memory area that is not used to store data. This
ensures that, when flushing the cache before a task switch, cached data items from the
old task are not transferred to the new task. These addresses must be valid and writable
in both the old and the new task's space. Any other usage of
flush
has undefined results.
Cache elements containing modified data are written back to memory by making two
passes, each of which references every 32nd byte of the reserved area with the
flush
instruction. Before the first pass, the RC field in
dirbase
is set to two and RB is set to
zero. This causes data-cache misses to flush element zero of each set. Before the second
pass, RB is changed to one, causing element one of each set to be flushed.
5-21
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