Intel i86W Manual page 78

CORE INSTRUCTIONS
5.11
CONTROL-TRANSFER INSTRUCTIONS
Control transfers can branch to any location within the address space. However, if a
relative branch offset, when added to the address of the control-transfer instruction plus
four, produces an address that is beyond the 32-bit addressing range of the i860 micro-
processor, the results are undefined.
Many of the control-transfer instructions are delayed transfers. They are delayed in the
sense that the i860 microprocessor executes one additional instruction following the
control-transfer instruction before actually transferring control. During the time used to
execute the additional instruction, the i860 microprocessor refills the instruction pipeline
by fetching instructions from the new instruction address. This avoids breaks in the
instruction execution pipeline.
It
is generally possible to find an appropriate instruction
to execute after the delayed control-transfer instruction even if it is merely the first
instruction of the procedure to which control is passed.
Programming Notes
The sequential instruction following a delayed control-transfer instruction may be nei-
ther another control-transfer instruction, nor a trap instruction, nor the target of a
control-transfer instruction.
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